X9521 datasheet(11/26 Pages) XICOR

11 / 26 page

REV 1.1.9 1/30/03

Characteristics subject to change without notice.

11 of 26

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X9521

– Preliminary Information

the Device Type Identiﬁer 1010111 or 1010010). Immedi-

ately after an operation to a DCP or CONSTAT Register is

performed, only a “Random EEPROM Read” is available.

Immediately following a “Random EEPROM Read” , a

“Current

EEPROM

Address

Read” or

“Sequential

EEPROM Read” is once again available (assuming that

no access to a DCP or CONSTAT Register occur in the

interim).

Random EEPROM Read

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master must

ﬁrst perform a “dummy” write operation. The master

issues the START condition and the Slave Address Byte,

receives an ACKNOWLEDGE, then issues an Address

Byte. This “dummy” Write operation sets the address

pointer to the address from which to begin the random

EEPROM read operation.

After the X9521 acknowledges the receipt of the Address

Byte, the master immediately issues another START con-

dition and the Slave Address Byte with the R/W bit set to

one. This is followed by an ACKNOWLEDGE from the

X9521 and then by the eight bit word. The master termi-

nates the read operation by not responding with an

ACKNOWLEDGE and instead issuing a STOP condition

(Refer to Figure 15.).

A similar operation called “Set Current Address” also

exists. This operation is performed if a STOP is issued

instead of the second START shown in Figure 15. In this

case, the device sets the address pointer to that of the

Address Byte, and then goes into standby mode after the

STOP bit. All bus activity will be ignored until another

START is detected.

Sequential EEPROM Read

Sequential reads can be initiated as either a current

address read or random address read. The ﬁrst Data Byte

is transmitted as with the other modes; however, the mas-

Slave

Address

Byte

Slave

Address

Data

SDA Bus

Signals from

the Slave

Signals from

the Master

Figure 15. Random EEPROM Address Read Sequence

0 1 0 0 0 0

1 0 1 0 0 0 0

READ Operation

WRITE Operation

“Dummy” Write

Data

(2)

Slave

Address

Data

(n)

SDA Bus

Signals from

the Slave

Signals from

the Master

Data

(n-1)

(n is any integer greater than 1)

Data

(1)

Figure 16. Sequential EEPROM Read Sequence

0 0 0

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