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WM8778EDS/R датащи(PDF) 19 Page - Wolfson Microelectronics plc

номер детали WM8778EDS/R
подробное описание детали  24 BIT 192KHZ STEREO CODEC
PDF  50 Pages
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производитель  WOLFSON [Wolfson Microelectronics plc]
домашняя страница  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8778EDS/R датащи(HTML) 19 Page - Wolfson Microelectronics plc

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WM8778
w
PP Rev 1.7 June 2004
19
I
2S MODE
In I
2S mode, the MSB of DIN is sampled by the WM8778 on the second rising edge of DACBCLK
following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on the
first falling edge of ADCBCLK following an ADCLRC transition and may be sampled on the rising
edge of ADCBCLK. ADCLRC and DACLRC are low during the left samples and high during the right
samples.
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
DACBCLK/
ADCBCLK
DIN/
DOUT
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 14 I
2S Mode Timing Diagram
DSP EARLY MODE
In DSP early mode, the MSB of DAC left data is sampled by the WM8778 on the second rising edge
on DACBCLK following a DACLRC rising edge. DAC right data follows DAC channel left data (Figure
15).
DACLRC
DACBCLK
DIN
Word Length (WL)
1/fs
LEFT CHANNEL
n
2
1
n-1
LSB
MSB
n
2
1
n-1
RIGHT CHANNEL
NO VALID DATA
1 BCLK
1 BCLK
Figure 15 DSP Early Mode Timing Diagram – DAC Data Input



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