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ZSC31014 датащи(PDF) 21 Page - Integrated Device Technology |
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ZSC31014 датащи(HTML) 21 Page - Integrated Device Technology |
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21 / 58 page ![]() ZSC31014 Datasheet © 2016 Integrated Device Technology, Inc. 21 January 20, 2016 I 2C™ is the protocol used during calibration (Command Mode). The ZSC31014 I2C™ slave address (00 HEX to 7FHEX) is selected by bits [9:3] of EEPROM word 02HEX. If the communication lock pattern Comm_lock (bits [5:3], EEPROM word 02HEX) is programmed to 011, the device will respond only to this address. Otherwise, the device will respond to all I 2C™ addresses. The factory setting for I2C™ slave address is 28 HEX with Comm_lock set. When programmed as an I 2C™ device, the INT/SS pin operates as an interrupt. The INT pin rises when new output data is ready and falls when the next I 2C™ communication occurs. It is most useful if the part is configured in Sleep Mode to indicate to the system that a new conversion is ready. See Figure 2.4 for the I 2C™ timing diagram and Table 2.7 for definitions of the parameters shown in the timing diagram. Table 2.7 I 2C™ Parameters PARAMETER SYMBOL MIN TYP MAX UNITS SCL clock frequency fSCL 100 400 kHz Start condition hold time relative to SCL edge tHDSTA 0.1 µs Minimum SCL clock low width 1) tLOW 0.6 µs Minimum SCL clock high width 1) tHIGH 0.6 µs Start condition setup time relative to SCL edge tSUSTA 0.1 µs Data hold time on SDA relative to SCL edge tHDDAT 0 µs Data setup time on SDA relative to SCL edge tSUDAT 0.1 µs Stop condition setup time on SCL tSUSTO 0.1 µs Bus free time between stop condition and start condition tBUS 2 µs 1) Combined low and high widths must equal or exceed minimum SCLK period. Figure 2.4 I 2C™ Timing Diagram (See section 3.1 for data transmission details.) SDA SCL tHDSTA tHDDAT tLOW tSUDAT tHIGH tSUSTA tHDSTA tSUSTO tBUS |
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