Data Sheet

ADRF5130

Rev. A | Page 7 of 10

THEORY OF OPERATION

The ADRF5130 requires a single-supply voltage applied to the

to minimize RF coupling.

ADRF5130. A small bypassing capacitor is recommended on

these digital signal lines to improve the RF signal isolation.

The ADRF5130 is internally matched to 50 Ω at the RF input

port (RFC) and the RF output ports (RF1 and RF2); therefore,

no external matching components are required. The RFx pins

are dc-coupled, and dc blocking capacitors are required on the

RF lines. The design is bidirectional; the input and outputs are

interchangeable.

The ideal power-up sequence of the ADRF5130 is as follows:

1. Connect to GND.

3. Power up the digital control input. Powering the digital

forward-bias and damage the ESD protection structures.

4. Power up the RF input. Depending on the logic level

RF1) is set to on mode, by which an insertion loss path is

provided from the input to the output, while the other RF

output port (for example, RF2) is set to off mode, by which

the output is isolated from the input.

Table 5. Switch Operation Mode

Switch Mode

RFC to RF1

RFC to RF2

0

Off mode: the RF1 port is isolated from the RFC

port and is internally terminated to a 50 Ω load to

absorb the applied RF signals.

On mode: a low insertion loss path from the RFC port

to the RF2 port.

1

On mode: a low insertion loss path from the RFC

port to the RF1 port.

Off mode: the RF2 port is isolated from the RFC port

and is internally terminated to a 50 Ω load to absorb

the applied RF signals.