For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

29

HMC701LP6CE

v09.1112

8 GHz 16-BIT FRACTIONAL-N PLL

Table 12. Reg 01h Enable & Reset Register

Bit

Type

Name

Width

Default

Description

0

r/W

malg_vcobuf_en

1

1

Vco Buffer Enable

1

r/W

mag_bias_en

1

1

Bias enable. When 0 PLL is disabled.

2

r/W

rfp_div_en

1

0

Enables / Holds refdiv in reset

Holding ref divider in reset is equivalent to

bypassing the divider, see Figure 4

3

r/W

xrefmux_todig_en

1

1

Enables clock gate for xtal muxed (sq or sin)

reference to digital.

Program 1

4

r/W

rfp_div_todig_en

1

1

Enables divided reference clock to the digital

see Figure 4

5

r/W

rfp_sqr_todig_en

1

0

Enables square wave xtal clock to main digital

see Figure 4. Program 0

6

r/W

rfp_sin_todig_en

1

0

Enables sine wave xtal clock to main digital

see Figure 4

7

r/W

rfp_buf_sq_en

1

1

Enables Square wave ref Buffer. also requires

reg3h[16]=0 for Square wave ref Buffer. See

Figure 4

8

r/W

rfp_buf_sin_en

1

0

Enables Sine wave ref Buffer. also requires

reg3h[16]=1 for Sine wave ref Buffer. See

Figure 4

9

r/W

vcop_todig_en

1

1

1= divided Vco as digital, Δ∑ modulator clock

0= Divided ref path as the Δ∑ modulator clock

Program 1

10

r/W

vcop_presc_en

1

1

Enables the prescaler bias

11

r/W

pfd_lkd_en

1

1

Enable / resetb to digital lockdetect circuit and

PFD’s lockdetect output gates

Program 1

12

r/W

cp_en

1

1

charge Pump Enable, disable is tri-stated output

13

r/W

dsm_rstb

1

1

1 - Enables fractional modulator

see also dsm_integer_mode Reg12h<3>

14

r/W

lkd_rstb

1

1

1 - enables lock detect circuit

15

r/W

pfds_rstb

1

1

cSP PFD FF rstb

1 - Enables the cycle Slip Prevention (cSP)

feature of the PFD

Table 13. Reg 02h Serial Data Out Force Register

Bit

Type

Name

Default

Description

0

r/W

malg_sdo_driver_force_val

1

LD/SDo Driver Enable control value (1=enabled).

Driver Enable controlled by this bit only when

reg02h[1]=1

1

r/W

malg_sdo_driver_force_en

1

When 1 LD/SDo Driver Enable controlled by reg

02h[0].

When 0 LD/SDo Driver Enable controlled by

internal SPi read active signal (ie. enabled only

when an SPi read occurs and high impedance all

other times)

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