For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

18

HMC701LP6CE

v09.1112

8 GHz 16-BIT FRACTIONAL-N PLL

Cycle Slip Prevention (CSP)

When changing frequencies the Vco is not yet locked to the reference and the phase difference at the PFD varies

rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with phase up to ±2π,

the gain of conventional PFDs will cycle from high gain, when the phase difference approaches a multiple of 2π, to

low gain, when the phase difference is slightly larger than a multiple of 0 radians. this phenomena is known as cycle

slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in

Figure 13. cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal

Laplace analysis.

the HMc701LP6cE PFD features cycle Slip Prevention (cSP), an ability to virtually eliminate cycle slipping during

acquisition. When enabled, the cSP feature essentially holds the PFD gain at maximum until such time as the

frequency difference is near zero. cSP allows significantly faster lock times as shown in Figure 13. the use of the

of PLL dynamics by adjusting the PFD sensitivity to cycle slipping. this is achieved by adjusting pfds_sat_deltaN

cSP will cause the Vco n divider to momentarily divide by a higher or lower n value in order to pull the divided Vco

phase back towards the reference edge. the maximum recommended Vco n divider deviation is no more than 20%

of the target n value. For example, if n=50 for the target frequency, then the cSP Magnitude should be 10 or less so

register 1ch Bits [3:0] would be programmed to ah.

in situations where the target n value is low, for example 36 the cSP behavior will be compromised because the

minimum Vco divide value is 32

Figure 13. Cycle Slip Prevention (CSP)

Charge Pump Gain

a simplified diagram of the charge pump is shown in Figure 14. charge pump up and down gains are set by cp_

value. Each of the UP and Dn charge pumps consist of 5-bit charge pumps with lsb of 125 µa. the current gain of the

pump, in amps/radian, is equal to the gain setting of this register divided by 2π.

For example if both cp_UPcurrent_sel and cp_DNcurrent_sel are set to ’01000’ the output current of each pump will

be 1ma and the gain Kp = 1ma/2π radians, or 159 ua/rad.

Charge Pump Gain Trim

in most applications Gain trim is not used. However it is available for special applications.

Each of the UP and Dn pumps may be trimmed separately to more precise values to improve current source matching

of the UP and Dn values, or to allow finer control of pump gain.

the pump trim controls are 3-bits, binary weighted for UP and Dn, in cp_UPtrim_sel and cp_DNtrim_sel respectively

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106

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