AD9371BBCZ datasheet(16/60 Pages) AD

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AD9371

Data Sheet

Rev. A | Page 16 of 60

Pin No.

Type1

Mnemonic

Description

H1, J1

TX2−, TX2+

Differential Output for Transmitter 2.

H11, H12, J3, J7, J8, J11, J12, K5 to K8,

K11, K12, L5, L6, L11, L12, M10, M11

I/O

GPIO_0 to GPIO_18

General-Purpose Inputs and Outputs Referenced to

VDD_IF. See Figure 4 to match the ball location to the

GPIO_x signal name.

H14, J14

TX1+, TX1−

Differential Output for Transmitter 1.

RESET

Active Low Chip Reset.

GP_INTERRUPT

General-Purpose Interrupt Signal.

TEST

Test Pin Used for JTAG Boundary Scan. Ground this pin if

unused.

I/O

SDIO

Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire

Mode.

J10

SDO

Serial Data Output.

K3, K4

SYSREF_IN+, SYSREF_IN−

LVDS SYSREF Clock Inputs for the JESD204B Interface.

SCLK

Serial Data Bus Clock.

K10

CSB

Serial Data Bus Chip Select. Active low.

L3, L4

SYNCINB1−, SYNCINB1+

LVDS Sync Signal Associated with ORx/Sniffer Channel

Data on the JESD204B Interface. Alternatively, these pins

can be set to a CMOS input using SYNCINB1+ as the input

and connecting SYNCINB1− with a 1 kΩ resistor to GND.

L7, L10

VSSD

Digital Ground.

L8, L9

VDIG

1.3 V Digital Core Supply. Use a separate trace on the PCB

back to a common supply point.

VCLK_VCO_LDO

Clock VCO LDO 1.1 V Output. Bypass this pin with a 1 µF

capacitor.

M3, M4

SYNCINB0−, SYNCINB0+

LVDS Sync Signal Associated with Rx Channel Data on the

JESD204B Interface. Alternatively, these pins can be set to

a CMOS input using SYNCINB0+ as the input and

connecting SYNCINB0− with a 1 kΩ resistor to GND.

RX1_ENABLE

Enables Rx Channel 1 Signal Path.

TX1_ENABLE

Enables Tx Channel 1 Signal Path.

RX2_ENABLE

Enables Rx Channel 2 Signal Path.

TX2_ENABLE

Enables Tx Channel 2 Signal Path.

M12

VDD_IF

CMOS/LVDS Interface Supply.

M13, M14

SYNCOUTB0+, SYNCOUTB0−

LVDS Sync Signal Associated with Transmitter Channel

Data on the JESD Interface. Alternatively, these pins can be

set to a CMOS output using SYNCOUTB0+ as the output

while leaving SYNCOUTB0− floating.

VDDA_CLK

1.3 V Clock Supply Input.

N3, N4

SERDOUT3−, SERDOUT3+

RF Current Mode Logic (CML) Differential Output 3. This

JESD204B lane can be used by the receiver data or by the

sniffer/observation receiver data.

N5, N6

SERDOUT2−, SERDOUT2+

RF CML Differential Output 2. This JESD204B lane can be

used by the receiver data or by the sniffer/observation

receiver data.

N8, P8

VDDA_SER

JESD204B 1.3 V Serializer Supply Input.

VDDA_DES

JESD204B 1.3 V Deserializer Supply Input.

N10, N11

SERDIN2−, SERDIN2+

RF CML Differential Input 2.

N12, N13

SERDIN3−, SERDIN3+

RF CML Differential Input 3.

P4, P5

SERDOUT1−, SERDOUT1+

RF CML Differential Output 1. This JESD204B lane can be

used by receiver data or by sniffer/observation receiver data.

P6, P7

SERDOUT0−, SERDOUT0+

RF CML Differential Output 0. This JESD204B lane can be

used by receiver data or by sniffer/observation receiver data.

JESD_VTT_DES

JESD204B Deserializer Termination Supply Input.

P11, P12

SERDIN0−, SERDIN0+

RF CML Differential Input 0.

P13, P14

SERDIN1−, SERDIN1+

RF CML Differential Input 1.

I is input, O is output, I/O is input/output, and N/A is not applicable.

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