AD9371BBCZ datasheet(58/60 Pages) AD

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AD9371

Data Sheet

Rev. A | Page 58 of 60

SYNTHESIZERS

RF PLL

The AD9371 contains three fractional-N PLLs to generate the

RF LOs used by the transmitter, receiver, and observation

receiver. The PLL incorporates an internal VCO and loop filter

that require no external components. The internal VCO LDO

regulators eliminate the need for additional external power

supplies for the PLLs. These regulators only require an external

bypass capacitor for each supply.

Clock PLL

The AD9371 contains a PLL synthesizer that generates all of the

baseband related clock signals and SERDES clocks. This PLL is

programmed based on the data rate and sample rate requirements

of the system.

External LO Inputs

The AD9371 provides two external LO inputs to allow an

external synthesizer to be used with the device. These inputs

must be 2× the desired LO frequency. Note that operation for

the external LO option is limited to a maximum of 4000 MHz.

One input pair is dedicated to the receiver LO generation circuit

and the other input provides the input to the transmitter and

observation receiver LO generation blocks. Note that the

observation receiver can obtain the LO from either the Tx LO

generator block or its own dedicated PLL. When the sniffer

channel is enabled, the LO for this block can only come from

the dedicated internal observation channel PLL.

SERIAL PERIPHERAL INTERFACE (SPI) INTERFACE

The AD9371 uses a SPI to communicate with the baseband

processor (BBP). This interface can be configured as a 4-wire

interface with dedicated receive and transmit ports, or it can be

configured as a 3-wire interface with a bidirectional data

communications port. This bus allows the BBP to set all device

control parameters using a simple address data serial bus protocol.

Write commands follow a 24-bit format. The first bit sets the

bus direction of the bus transfer. The next 15 bits set the address

where data is written. The final eight bits are the data being

transferred to the specific register address.

Read commands follow a similar format with the exception that

the first 16 bits are transferred on the SDIO pin, and the final

eight bits are read from the AD9371, either on the SDO pin in

4-wire mode or on the SDIO pin in 3-wire mode.

GPIO_x AND GPIO_3P3_x PINS

The AD9371 general-purpose input/output signals referenced

to the VDD_IF supply can be configured for numerous functions.

Some of these pins, when configured as outputs, are used by the

BBP as real-time signals to provide a number of internal settings

and measurements. This configuration allows the BBP to monitor

receiver performance in different situations. A pointer register

selects what information is output to these pins. Signals used for

manual gain mode, calibration flags, state machine states, and

various receiver parameters are among the outputs that can be

monitored on these pins. In addition, certain pins can be

configured as inputs and used in various functions such as

setting the receiver gain in real time.

The GPIO_3P3_x pins referenced to the VDDA_3P3 supply are

also included in the device and can provide control signals to

the external components such as VGAs or attenuators in the RF

section that typically use a higher reference voltage.

AUXILIARY CONVERTERS

Auxiliary ADC Inputs (AUXADC_x)

The AD9371 contains an auxiliary ADC that is multiplexed to four

input pins (AUXADC_0 through AUXADC_3). This block can

monitor system voltages without adding additional components.

The auxiliary ADC is 12 bits with an input voltage range of 0.05 V

to VDDA_3P3 − 0.25 V. When enabled, the auxiliary ADC is

free running. Software reads of the output value provide the last

value latched at the ADC output.

Auxiliary DACs (AUXDAC_x)

The AD9371 contains 10 identical auxiliary DACs (AUXDAC_0

to AUXDAC_9) that can supply bias voltages, analog control

voltages, or other system functionality. The inputs of these auxiliary

DACs (AUXDAC_0 to AUXDAC_9) are multiplexed with the

GPIO_3P3_x pins according to Table 7. The auxiliary DACs are

10 bits and have an output voltage range of approximately 0.5 V

to VDDA_3P3 − 0.3 V and have a current drive of 10 mA.

Table 7. AUXDAC Input Pin Assignments

GPIO_3P3 Pin

AUXDAC Output

GPIO_3P3_9

AUXDAC_0

GPIO_3P3_7

AUXDAC_1

GPIO_3P3_6

AUXDAC_2

GPIO_3P3_10

AUXDAC_3

GPIO_3P3_0

AUXDAC_4

GPIO_3P3_1

AUXDAC_5

GPIO_3P3_3

AUXDAC_6

GPIO_3P3_4

AUXDAC_7

GPIO_3P3_5

AUXDAC_8

GPIO_3P3_8

AUXDAC_9

JESD204B DATA INTERFACE

The digital data interface for the AD9371 uses JEDEC Standard

JESD204B Subclass 1. The serial interface operates at speeds of

up to 6144 Mbps. The benefits of the JESD204B interface include a

reduction in required board area for data interface routing and

smaller package options due to the need for fewer pins. Digital

filtering is included in all receiver and transmitter paths to provide

proper signal conditioning and sampling rates to meet the

JESD204B data requirements. Examples of the digital filtering

configurations for the Tx and Rx paths are shown in Figure 240

and Figure 241, respectively.

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