LPC2290 datasheet(26/41 Pages) PHILIPS

26 / 41 page

Philips Semiconductors

LPC2290

16/32-bit ARM microcontrollers with external memory interface

Preliminary data

Rev. 01 — 09 February 2004

26 of 41

9397 750 12874

operation resumed by either a Reset or certain speciﬁc interrupts that are able to

function without clocks. Since all dynamic operation of the chip is suspended,

Power-down mode reduces chip power consumption to nearly zero.

A Power Control for Peripherals feature allows individual peripherals to be turned off if

they are not needed in the application, resulting in additional power savings.

6.20.7

VPB bus

The VPB Divider determines the relationship between the processor clock (cclk) and

the clock used by peripheral devices (PCLK). The VPB Divider serves two purposes.

The ﬁrst is that the VPB bus cannot operate at the highest speeds of the CPU. In

order to compensate for this, the VPB bus may be slowed down to one half or one

fourth of the processor clock rate. The default condition at reset is for the VPB bus to

run at one quarter of the CPU clock. The second purpose of the VPB Divider is to

allow power savings when an application does not require any peripherals to run at

the full processor rate. Because the VPB Divider is connected to the PLL output, the

PLL remains active (if it was running) during Idle mode.

6.21 Emulation and debugging

The LPC2290 supports emulation and debugging via a JTAG serial port. A trace port

allows tracing program execution. Debugging and trace functions are multiplexed only

with GPIOs on Port 1. This means that all communication, timer and interface

peripherals residing on Port 0 are available during the development and debugging

phase as they are when the application is run in the embedded system itself.

6.21.1

Embedded ICE™

Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging

of the target system requires a host computer running the debugger software and an

EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the

Remote Debug Protocol commands to the JTAG data needed to access the ARM

core.

The ARM core has a Debug Communication Channel function built-in. The debug

communication channel allows a program running on the target to communicate with

the host debugger or another separate host without stopping the program ﬂow or

even entering the debug state. The debug communication channel is accessed as a

co-processor 14 by the program running on the ARM7TDMI-S core. The debug

communication channel allows the JTAG port to be used for sending and receiving

data without affecting the normal program ﬂow. The debug communication channel

data and control registers are mapped in to addresses in the EmbeddedICE™ logic.

6.21.2

Embedded trace

Since the LPC2290 has signiﬁcant amounts of on-chip memory, it is not possible to

determine how the processor core is operating simply by observing the external pins.

The Embedded Trace Macrocell provides real-time trace capability for deeply

embedded processor cores. It outputs information about processor execution to the

trace port.

The ETM is connected directly to the ARM core and not to the main AMBA system

bus. It compresses the trace information and exports it through a narrow trace port.

An external trace port analyzer must capture the trace information under software

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