P83C266BDR datasheet(82/92 Pages) PHILIPS

82 / 92 page

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−

n.c.

−−

−

P5.6

I/O

CMOS

open-drain

Yes

original state

Z(2)

PWM5

−

open-drain

Yes

LOW

−

P5.7

I/O

CMOS

open-drain

Yes

original state

Z(2)

PWM6

−

open-drain

Yes

LOW

−

P3.0

I/O

CMOS + Rpu(3) open-drain

Yes

original state

Z(2)

ADC0

analog

−−

−

PH1SEM

−

open-drain, 2 mA

note 4

−−

−

S1ESEM

−

open-drain, 2 mA

note 4

−−

P3.1

I/O

CMOS + Rpu(3) open-drain

Yes

original state

Z(2)

ADC1

analog

−−

−

P2.0

I/O

CMOS

open-drain + Rpu(5) Yes

−−

P3.2

I/O

CMOS + Rpu(3) open-drain

Yes

original state

Z(2)

ADC2

analog

−−

−

P2.1

I/O

CMOS

open-drain + Rpu(5) Yes

−−

P3.3

I/O

CMOS

open-drain

Yes

original state

Z(2)

PWM7

−

open-drain

Yes

LOW

−

P2.2

I/O

CMOS

open-drain + Rpu(5) Yes

−−

−

P2.3

I/O

CMOS

open-drain + Rpu(5) Yes

−−

P0.0

I/O

CMOS

open-drain

Yes

original state

Z(2)

P0.1

I/O

CMOS

open-drain

Yes

original state

Z(2)

P0.2

I/O

CMOS

open-drain

Yes

original state

Z(2)

−

OSD_EPR_TST

−−

−

n.c.

−−

−

P0.3

I/O

CMOS

open-drain

Yes

original state

Z(2)

P0.4

I/O

CMOS

open-drain

Yes

original state

Z(2)

P0.5

I/O

CMOS

open-drain

Yes

original state

Z(2)

P0.6

I/O

CMOS

open-drain

Yes

original state

Z(2)

P0.7

I/O

CMOS

open-drain

Yes

original state

Z(2)

−

VDDD

−−

−

VSSD

−−

−

SYMBOL

TYPE

INPUT LEVEL

OUTPUT TYPE

SLOPE

CONTROL

OUTPUT IN

IDLE MODE

OUTPUT

AFTER RESET

ACTIVE STATE

SW CONTROL

SDIP42

PLCC68

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