PPC34C60 datasheet(44/58 Pages) SMSC

44 / 58 page

SMSC DS – PPC34C60

Page 44

Rev. 06/01/2001

ADVANCED INFORMATION

FIGURE 15 - EPP ADDRESS WRITE (PARALLEL PORT SIGNALS)

EPP timing is IEEE P1284 compatible except the PPC34C60:

Does not use nINIT to terminate EPP Mode (return to compatibility mode)

Does not support using nACK to generate interrupts to the Host while selected.

See EPP Address Write Timing Parameters.

EPP ADDRESS WRITE (PARALLEL PORT SIGNALS)

PARAMETER

MIN

TYP

MAX

UNITS

The Host asserts nSTB. At the same time the Host

places the address byte on HD[0:7]. This specifies the

jitter between nSTB being asserted and an address

appearing on HD[0:7]. The PPC34C60 does not rely

on nSTB.

The nSLCTIN signal is asserted coincident with the

above events to indicate that an EPP address cycle is

to take place. This time represents the jitter margin

between nSLCTIN asserted and the above two events.

The PPC34C60 will detect the assertion of nSLCTIN

and will assert BSY to indicate that it has latched the

address on HD[0:7].

250

[6 SCLK]

10,000

After the PPC34C60 asserts BSY the Host will then

indicate that the cycle is complete by deasserting

nSLCTIN.

This represents the response time

requirements put on the Host.

[SCLK]

Seeing that the Host has indicated that the cycle is

complete, the PPC34C60 will then deassert the BSY

line as soon as it is ready for another EPP transfer.

209

[5 SCLK]

As soon as the PPC34C60 deasserts BSY the Host

may initiate another EPP transfer. This time represents

the time between the PPC34C60 deasserting BSY to

the Host starting a new transfer cycle.

VALID ADDRESS

HD[0:7]

nSTB H

nALF H

nSLCTIN H

nINIT H

BSY P

nACK P

PE P

SLCL P

nERR P

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