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PPC34C60 датащи(PDF) 37 Page - SMSC Corporation

номер детали PPC34C60
подробное описание детали  PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
PDF  58 Pages
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производитель  SMSC [SMSC Corporation]
домашняя страница  http://www.smsc.com
Logo SMSC - SMSC Corporation

PPC34C60 датащи(HTML) 37 Page - SMSC Corporation

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SMSC DS – PPC34C60
Page 37
Rev. 06/01/2001
ADVANCED INFORMATION
ECP Mode
The ECP interface requests a reverse transfer by disabling the data line drivers, then lowering Inet (HINIT). The
PPC34C60 acknowledges the reverse transfer by lowering PError (HPE), and driving the data lines. When the PPC34C60
has data ready, it will lower Ack (HACK). The ECP chip will respond by raising Auto LF (HALF). The PPC34C60 then
raises Ack, signaling the ECP chip to latch the data. The ECP chip then terminates the cycle by lowering Auto LF.
TIMING SYMBOL
PPC34C60 PIN NAME
PIN NUMBER
HD[0:7]
HD[0:7]
5,8,13,15-18,20
nSTB
nHSTB
2
nALF
nHALF
3
nSEL
nHSEL
14
nINIT
nHINIT
11
BSY
HBSY
26
nACK
nHACK
24
PE
HPE
28
SLCT
HSLCT
30
nERR
nHERR
6
FIGURE 11 - SPP ADDRESS WRITE TIMING (PARALLEL PORT SIGNALS)
All timing for SCLK = 24MHz.
This signaling sequence pertains to a device that has been previously selected to communicate via SPP Mode. This timing
sequence is not specified in the P1284 specification; it should not violate the P1284 spec.
See SPP Address Write Timing Parameters.
t1
t5
t6
t2
t4
t3
HD[0:7]
nSTB H
nALF H
nSEL H
nINIT H
BSY P
nACK P
PE P
SLCT P
nERR P



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