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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AM79C970 датащи(PDF) 130 Page - Advanced Micro Devices |
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AM79C970 датащи(HTML) 130 Page - Advanced Micro Devices |
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130 / 168 page  P R E L I M I N A R Y AMD 1-997 Am79C970 Register Summary PCI Configuration Registers Note: RO = read only, RW = read/write, U = undefined value Offset Name Width in Bit Access Mode Default Value 00h Vendor ID 16 RO 1022h 02h Device ID 16 RO 2000h 04h Command 16 RW uuuu 06h Status 16 RW uuuu 08h Revision ID 8 RO 00h 09h Programming IF 8 RO 00h 0Ah Sub-Class 8 RO 00h 0Bh Base-Class 8 RO 02h 0Dh Latency Timer 8 RO 00h 0Eh Header Type 8 RO 00h 10h Base Address 32 RW uuuu uuuu 3Ch Interrupt Line 8 RW uu 3Dh Interrupt Pin 8 RO 01h Control and Status Registers Note: u = undefined value, R = Running register, S = Setup register, T = Test register Default Value After RAP Addr Symbol H_RESET Comments Use 00 CSR0 uuuu 0004 PCnet-PCI Status Register R 01 CSR1 uuuu uuuu IADR[15:0]: Base Address of INIT Block Lower S 02 CSR2 uuuu uuuu IADR[31:16]: Base Address of INIT Block Upper S 03 CSR3 uuuu 0000 Interrupt Masks and Deferral Control S 04 CSR4 uuuu 0115 Test and Features Control R 05 CSR5 uuuu 0000 Reserved T 06 CSR6 uuuu uuuu RXTX: RX/TX Descriptor Table Lengths T 07 CSR7 uuuu 0000 Reserved T 08 CSR8 uuuu uuuu LADR0: Logical Address Filter — LADRF[15:0] T 09 CSR9 uuuu uuuu LADR1: Logical Address Filter — LADRF[31:16] T 10 CSR10 uuuu uuuu LADR2: Logical Address Filter — LADRF[47:32] T 11 CSR11 uuuu uuuu LADR3: Logical Address Filter — LADRF[63:48] T 12 CSR12 uuuu uuuu PADR0: Physical Address Register — PADR[15:0] T 13 CSR13 uuuu uuuu PADR1: Physical Address Register — PADR[31:16] T 14 CSR14 uuuu uuuu PADR2: Physical Address Register — PADR[47:32] T 15 CSR15 see reg. desc. MODE: Mode Register S 16 CSR16 uuuu uuuu IADR[15:0]: Alias of CSR1 T 17 CSR17 uuuu uuuu IADR[31:16]: Alias of CSR2 T 18 CSR18 uuuu uuuu CRBAL: Current RCV Buffer Address Lower T 19 CSR22 uuuu uuuu CRBAU: Current RCV Buffer Address Upper T 20 CSR20 uuuu uuuu CXBAL: Current XMT Buffer Address Lower T 21 CSR21 uuuu uuuu CXBAU: Current XMT Buffer Address Upper T |
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