PRELIMINARY SPECIFICATION

64COM/128SEG DRIVE FOR DOT MATRIX LCD

KS0708

14

M/M-96-D001

97-09-19

Data Tramsfer

To match the timing of the display data RAM and registers to that of the controlling microprocessor,

KS0708 uses an internal data bus and bus buffer. When the microprocessor reads the contents of display

data RAM, the data for the initial read cycle is first stored inthe bus buffer (dummy read cycle). On the next

read cycle, the data is read from the bus buffer onto the microprocessor bus. At the same time, the next

block of data is transferred from RAM to the bus buffer. Otherwise, when the microprocessor write data to

display data RAM. the data is written to RAM atfer the falling edge of £àE£§. Therefore, it is necessary to

check Busy Flag to write or read the next data. (refer to Figure4, 5)

Page Address Register

The 3-bit Page Address register provides the page address to display data RAM (refer to Figure 3). The

microprocessor issues Set Page Address instruction to change the page and to access another page.

Column Address Counter

The column address counter is a 6-bit presettable counter that provides column address to display data

RAM (refer to Figure 3). It is incremented by 1 automatically after execution of each Read/Write Data

instruction. The column address counter loops the values 0 to 127, and it is independent of page address

register. The ADC pin is issued to change the relationship between RAM Column address and display seg-

ment output.

Display Start Line Register

The display start line register stores the line address of display data RAM that corresponds to the first (nor-

mally the top) line(COM1) of liquid crystal display(LCD) panel. See Figure 3. When displaying contents in

display data RAM on the LCD panel, 6-bit data(DB[5:0]) of the Set Display Start Line is latched in display

start line register. Latched data are transferred to the line address counter just before COM1 is active High,

presetting the line address counter. The line counter is then incremented on the display latch clock signal

once for every display line. It is used for vertical scrolling of the liquid crystal display screen.