PRELIMINARY SPECIFICATION

64COM/128SEG DRIVE FOR DOT MATRIX LCD

KS0708

10

M/M-96-D001

97-09-19

Display Data RAM

The Display Data RAM stores pixel data for the LCD. It is a 128-column x 64-row addressable array as

shown in Figure 3. The 64 rows are divided into 8 pages of 8 lines. Data is read from or written to the 8

lines of each page directly through DB0 to DB7.

The microprocessor reads from and writes to RAM through the I/O buffer. Since the LCD controller oper-

ates independently, data can be written to RAM at the same time as data is being displayed, without caus-

ing the LCD to flick.

DB0

1

0

0

0

1

DB1

1

0

0

1

0

DB2

1

0

1

0

0

DB3

1

1

0

0

0

DB4

1

0

1

0

0

DB5

1

0

0

1

0

DB6

1

0

0

0

1

DB7

0

0

0

0

0

( Display Data RAM )

COM1

COM2

COM3

COM4

COM5

COM6

COM7

COM8

( LCD Panel )

Figure 2. RAM-to-LCD data transfer