AD7616BSTZ datasheet(29/51 Pages) AD

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AD7616

Data Sheet

Rev. 0 | Page 28 of 50

DEVICE CONFIGURATION

OPERATIONAL MODE

The mode of operation, hardware mode or software mode, is

configured when the AD7616 is released from full reset. The

logic level of the HW_RNGSELx pins when the RESET pin

transitions from low to high determines the operational mode. The

HW_RNGSELx pins are dual function. If HW_RNGSELx = 0b00,

the AD7616 enters software mode. Any other combination of

the HW_RNGSELx configures the AD7616 to hardware mode and

the analog input range is configured as per Table 8. After software

mode is configured, the logic level of the HW_RNGSELx signals is

ignored. After an operational mode is configured, a full reset via

the RESET pin is required to exit the operational mode and to set

up an alternative mode. If hardware mode is selected, all further

device configuration is via pin control. Access to the on-chip

registers is prohibited in hardware mode. In software mode, the

interface and reference configuration must be configured via

pin control but all further device configuration is via register

access only.

INTERNAL/EXTERNAL REFERENCE

The internal reference is enabled or disabled when the AD7616

is released from a full reset. The logic level of the REFSEL signal

when the RESET pin transitions from low to high configures the

reference. After the reference is configured, changes to the logic

level of the REFSEL signal are ignored. If the REFSEL signal is

set to 1, the internal reference is enabled. If REFSEL is set to

Logic 0, the internal reference is disabled and an external

reference must be supplied to the REFINOUT pin for correct

operation of the AD7616. A full reset via the RESET pin is required

to exit the operational mode and set up an alternative mode.

Connect a 100 nF capacitor between the REFINOUT and

REFINOUTGND pins. If using an external reference, place a

10 kΩ band limiting resistor in series between the reference and

the REFINOUT pin of the AD7616.

DIGITAL INTERFACE

The digital interface selection, parallel or serial, is configured

when the AD7616 is released from a full reset. The logic level of

the SER/PAR signal when the RESET pin transitions from low

to high configures the interface. If the SER/PAR signal is set to 0,

the parallel interface is enabled. If the SER/PAR signal is set to 1,

the serial interface is selected. Additionally, if the serial interface

is selected, the SER1W signal is monitored when the RESET pin is

released to determine if serial 1-wire or 2-wire mode is selected.

After the interface is configured, changes to the logic level of the

SER/PAR signal or the SER1W signal (when the serial interface is

enabled) are ignored. A full reset via the RESET pin is required

to exit the operation mode and set up an alternative mode.

HARDWARE MODE

If hardware mode is selected, the available functionality is

restricted and all functionality is configured via pin control.

The logic level of the following signals is checked after a full

reset to configure the functionality of the AD7616: CRC,

BURST, SEQEN, and OSx. Table 11 provides a summary of the

signals that are latched by the device on the release of a full

reset, depending on the mode of operation chosen. After the

device is configured, a full reset via the RESET pin is required to

exit the configuration and set up an alternative configuration.

Functionality availability is restricted depending on the interface

type selected. See Table 10 for a full list of the functionality

available in hardware parallel or serial mode.

The CHSELx pins are queried at reset to determine the initial

analog input channel pair to acquire for conversion or to configure

the initial settings for the sequencer. The channel pair selected

for conversion or the hardware sequencer can be reconfigured

during normal operation by setting and maintaining the

CHSELx signal level before the CONVST rising edge until the

BUSY falling edge.

The HW_RNGSELx signals control the analog input range for

all 16 analog input channels. A logic change on these pins has an

immediate effect on the analog input range; however, the typical

settling time is approximately 120 µs, in addition to the normal

acquisition time requirement. The recommended practice is to

hardwire the range select pins according to the desired input

range for the system signals.

Access to the on-chip registers is prohibited in hardware mode.

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