AD7616BSTZ datasheet(34/51 Pages) AD

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Data Sheet

AD7616

Rev. 0 | Page 33 of 50

SERIAL INTERFACE

To interface to the AD7616 over the SPI, the SER/PAR pin must

be tied high. The CS and SCLK signals transfer data from the

AD7616. The AD7616 has two serial data output pins, SDOA

and SDOB. Data is read back from the AD7616 using serial

1-wire or serial 2-wire mode.

In serial 2-wire mode for the AD7616, conversion results from

Channel V0A to Channel V7A appear on SDOA, and conversion

results from Channel V0B to Channel V7B appear on SDOB.

In serial 1-wire mode, conversion results from Channel V0B

to Channel V7B are interlaced with conversion results from

Channel V0A to Channel V7A. To achieve the maximum

throughput, it is required to use 2-wire mode.

To read back data over both SDOA and SDOB, the SER1W pin

must be tied high. If data is to be read back over SDOA only, the

SER1W pin must be tied low. Serial 1-wire or 2-wire mode is

configured when the AD7616 is released from full reset.

Reading Conversion Results

The CONVST signal initiates the conversion process. A low to

high transition on the CONVST signal initiates a conversion of

the selected inputs. The BUSY signal goes high to indicate a

conversion is in progress. When the BUSY signal transitions

from high to low to indicate that a conversion is complete, it is

possible to read back conversion results on the serial interface.

The CS falling edge takes the data output lines, SDOA and SDOB,

out of three-state and clocks out the MSB of the conversion

result. The rising edge of SCLK clocks all subsequent data bits

onto the serial data outputs, SDOA and SDOB. Figure 57 shows

a read of two simultaneous conversion results using two SDOx

lines on the AD7616. If the status register is appended to the

conversion results or operating in sequencer burst mode where

multiples of 16 SCLK transfers access data from the AD7616,

hold CS low to frame the entire data. Data can also be clocked

out using just one SDOx line, in which case SDOA must be used

to access all conversion data. For the AD7616 to access both

Channel VxA and Channel VxB conversion results on one

SDOx line, a total of 32 SCLK cycles is required. Frame these

32 SCLK cycles using one CS signal, or individually frame each

group of 16 SCLK cycles using the CS signal. The disadvantage

of using just one SDOx line is that the throughput rate is reduced.

Leave the unused SDOB line unconnected in serial 1-wire

mode. If using SDOA as a single serial data output line, the

channel results are output in the following order: VxA and VxB.

Figure 58 shows a 1-wire, serial readback operation.

The speed at which the data can be read back in serial interface

mode is dependent on SPI frequency, VDRIVE supply, and the

capacitance of the load on the SDO line, CLOAD. Table 14 shows a

summary of the maximum speed achievable for various conditions.

Table 14. SPI Frequency vs. Load Capacitance and VDRIVE

VDRIVE (V)

CLOAD (pF)

SPI Frequency (MHz)

2.3 to 3

3 to 3.6

Figure 57. Serial Interface, 2-Wire Mode

Figure 58. Serial Interface, 1-Wire Mode

CONVST

BUSY

141516

SCLK

SDOA

DB15

DB14

DB13

DB2

DB1

DB0

DB15

DB14

DB13

DB2

DB1

DB0

SDOB

CHANNEL VAx RESULT

CHANNEL VBx RESULT

CONVST

BUSY

SCLK

DB15

DB14

DB1

DB0

DB15

DB14

DB1

DB0

SDOA

CHANNEL VAx RESULT

CHANNEL VBx RESULT

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