MCP6V92 datasheet(20/48 Pages) MICROCHIP

20 / 48 page

MCP6V91/1U/2/4

DS20005434B-page 20

 2015-2016 Microchip Technology Inc.

4.2.1.3

Input Current Limits

In order to prevent damage and/or improper operation

of these amplifiers, the circuit must limit the currents

into the input pins (see Section 1.1 “Absolute

Maximum

Ratings †”).

This

requirement

independent of the voltage limits discussed previously.

Figure 4-6 shows one approach to protecting these

inputs. The R1 and R2 resistors limit the possible

current in or out of the input pins (and into D1 and D2).

The diode currents will dump onto VDD.

FIGURE 4-6:

Protecting the Analog Inputs

Against High Currents.

It is also possible to connect the diodes to the left of the

R1 and R2 resistors. In this case, the currents through

the D1 and D2 diodes need to be limited by some other

mechanism. The resistors then serve as in-rush current

limiters; the DC current into the input pins (VIN+ and

VIN-) should be very small.

A significant amount of current can flow out of the

inputs (through the ESD diodes) when the common-

mode input voltage (VCM) is below ground (VSS) (see

Figure 2-18).

4.2.2

RAIL-TO-RAIL OUTPUT

The output voltage range of the MCP6V91/1U/2/4

zero-drift op amps is VDD – 9 mV (typical) and

VSS +7 mV (typical) when RL =10kΩ is connected to

VDD/2 and VDD = 5.5V. Refer to Figures 2-20 and 2-21

for more information.

This op amp is designed to drive light loads; use

another amplifier to buffer the output from heavy loads.

4.3

Application Tips

4.3.1

INPUT OFFSET VOLTAGE OVER

TEMPERATURE

Table 1-1 gives both the linear and quadratic

temperature coefficients (TC1 and TC2) of input offset

voltage. The input offset voltage, at any temperature in

the specified range, can be calculated as follows:

EQUATION 4-1:

4.3.2

DC GAIN PLOTS

Figures 2-10 to 2-12 are histograms of the reciprocals

(in units of µV/V) of CMRR, PSRR and AOL,

respectively. They represent the change in input offset

voltage (VOS) with a change in common-mode input

voltage (VCM), power supply voltage (VDD) and output

voltage (VOUT). The histograms are based on data

taken with the production test equipment and the

results reflect the trade-off between accuracy and test

time. The actual performance of the devices is typically

higher than shown in Figures 2-10 to 2-12.

The 1/AOL histogram is centered near 0 µV/V because

the measurements are dominated by the op amp’s

input noise. The negative values shown represent

noise and tester limitations, not unstable behavior.

Production tests make multiple VOS measurements,

which validates an op amp's stability; an unstable part

would show greater VOS variability or the output would

stick at one of the supply rails.

4.3.3

OFFSET AT POWER-UP

When these parts power up, the input offset (VOS) starts

at its uncorrected value (usually less than ±5 mV).

Circuits with high DC gain can cause the output to reach

one of the two rails. In this case, the time to a valid

output is delayed by an output overdrive time (like tODR)

in addition to the start-up time (like tSTR).

It can be simple to avoid this extra start-up time.

Reducing the gain is one method. Adding a capacitor

across the feedback resistor (RF) is another method.

VDD

min(R1,R2)>

VSS –min(V1,V2)

2mA

VOUT

min(R1,R2)>

max(V1,V2)– VDD

2mA

MCP6V9X

VOS TA



VOS TC1TTC2T

Where:

T=TA –25°C

VOS(TA) = Input offset voltage at TA

VOS = Input offset voltage at +25°C

TC1 = Linear temperature coefficient

TC2 = Quadratic temperature coefficient

MCP6V92 датащи(PDF) 20 Page - Microchip Technology

MCP6V92 датащи(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL