LAN9250 datasheet(150/421 Pages) MICROCHIP

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LAN9250

DS00001913A-page 150

 2015 Microchip Technology Inc.

11.6.4

MAGIC PACKET DETECTION

Setting the Magic Packet Enable bit (MPEN) in the Host MAC Wake-up Control and Status Register (HMAC_WUCSR)

places the Host MAC in the “Magic Packet” detection mode. In this mode, normal data reception is disabled, and detec-

tion logic within the Host MAC examines received data for a Magic Packet.

Upon detection, the Magic Packet Received bit (MPR) in the HMAC_WUCSR register is set. When the host clears the

MPEN bit, the Host MAC will resume normal receive operation.

In Magic Packet mode, the Host MAC constantly monitors each frame addressed to the node for a specific Magic Packet

pattern. Only packets passing the Address Filtering check of Section 11.4 (see Note 6) are checked for the Magic Packet

requirements. Once the address requirement has been met, the Host MAC checks the received frame for the pattern

48’hFF_FF_FF_FF_FF_FF after the destination and source address field. The Host MAC then looks in the frame for 16

repetitions of the Host MAC address without any breaks or interruptions. In case of a break in the 16 address repetitions,

the Host MAC again scans for the 48'hFF_FF_FF_FF_FF_FF pattern in the incoming frame. The 16 repetitions may be

anywhere in the frame but must be preceded by the synchronization stream. The device will also accept a multicast

frame, as long as it detects the 16 duplications of the Host MAC address.

For example, if the Host MAC address is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence

in an Ethernet frame:

Destination Address Source Address ……………FF FF FF FF FF FF

00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55

…CRC

Note 6:

Normally, for Magic Packet Detection, address filtering should be set for Perfect Filtering or Hash Perfect

Filtering.

11.7

Receive Checksum Offload Engine (RXCOE)

The receive checksum offload engine provides assistance to the Host by calculating a 16-bit checksum for a received

Ethernet frame. The RXCOE readily supports the following IEEE802.3 frame formats:

• Type II Ethernet frames

• SNAP encapsulated frames

• Support for up to 2, 802.1q VLAN tags

The resulting checksum value can also be modified by software to support other frame formats.

The RXCOE has two modes of operation. In mode 0, the RXCOE calculates the checksum between the first 14 bytes

of the Ethernet frame and the FCS. This is illustrated in Figure 11-2.

In mode 1, the RXCOE supports VLAN tags and a SNAP header. In this mode, the RXCOE calculates the checksum at

the start of L3 packet. The VLAN1 tag register is used by the RXCOE to indicate what protocol type is to be used to

indicate the existence of a VLAN tag. This value is typically 8100h.

Example frame configurations:

FIGURE 11-2:

RXCOE CHECKSUM CALCULATION

DST

SRC

Frame Data

Calculate Checksum

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