LAN9250 datasheet(147/421 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001913A-page 147

LAN9250

The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether or not this is a

Wakeup Frame. Table 11-3, describes the byte mask’s bit fields.

Filter x Mask 0 corresponds to bits [31:0]. Where the lsb corresponds to the first byte on the wire.

Filter x Mask 1 corresponds to bits [63:32]. Where the lsb corresponds to the first byte on the wire.

Filter x Mask 2 corresponds to bits [95:64]. Where the lsb corresponds to the first byte on the wire.

Filter x Mask 3 corresponds to bits [127:96]. Where the lsb corresponds to the first byte on the wire.

The following tables define elements common to both WUFF register structures.

The Filter i command register controls Filter i operation. Table 11-4 shows the Filter I command register.

The Filter i Offset register defines the offset in the frame’s destination address field from which the frames are examined

by Filter i. Table 11-5 describes the Filter i Offset bit fields.

Filter 5 CRC-16

Filter 4 CRC-16

Filter 7 CRC-16

Filter 6 CRC-16

TABLE 11-3:

FILTER I BYTE MASK BIT DEFINITIONS

Filter i Byte Mask Description

Bits

Description

127:0

Byte Mask:

If bit j of the byte mask is set, the CRC machine processes byte pattern-offset + j of the

incoming frame. Otherwise, byte pattern-offset + j is ignored.

TABLE 11-4:

FILTER I COMMAND BIT DEFINITIONS

Filter i Commands

Bits

Description

3:2

Address Type:

Defines the destination address type of the pattern.

00 = Pattern applies only to unicast frames.

10 = Pattern applies only to multicast frames.

X1 = Pattern applies to all frames that have passed the regular receive filter.

RESERVED

Enable Filter:

When bit is set, Filter i is enabled, otherwise, Filter i is disabled.

TABLE 11-2:

WAKEUP FRAME FILTER REGISTER STRUCTURE (CONTINUED)

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