LAN9250 datasheet(144/421 Pages) MICROCHIP

144 / 421 page

LAN9250

DS00001913A-page 144

 2015 Microchip Technology Inc.

11.5

Frame Filtering

Following the address filtering, frames are accepted or rejected according to the following:

• Good frames that pass the address filtering are accepted. In the RX Status for these frames, the Filtering Fail bit

will be clear (since the frame passed the address filter). The Packet Filter bit will be set.

• Good frames that fail the address filtering are accepted if the Receive All Mode (RXALL) bit in the Receive Config-

uration Register (RX_CFG) is set. In the RX Status for these frames, the Filtering Fail bit will be set (since the

frame failed the address filter). The Packet Filter bit will also be set (since the RXALL bit allowed the acceptance

of the frame).

• A good Broadcast frame is accepted if it passes the address filtering or if the RXALL bit is set. The Disable Broad-

cast Frames (BCAST) bit in the Receive Configuration Register (RX_CFG) determines if the Packet Filter bit in the

RX Status is set (BCAST=0) or cleared (BCAST=1). Note that Disable Broadcast Frames (BCAST) doesn’t cause

the frame to be dropped if it passes the address filtering or if the RXALL bit is set. The Filtering Fail bit will indicate

if the address filtering passed or failed.

• A good Control frame is accepted if it passes the address filtering or if the RXALL bit is set. The Pass Control

Frames (FCPASS) bit in the Host MAC Flow Control Register (HMAC_FLOW) determines if the Packet Filter bit in

the RX Status is set (FCPASS=1) or cleared (FCPASS=0). Note that Pass Control Frames (FCPASS) being low

doesn’t cause the frame to be dropped if it passes the address filtering or if the RXALL bit is set. The Filtering Fail

bit will indicate if the address filtering passed or failed.

• A frame that has an error (runt, collision, CRC, too long) and is greater than 60 bytes in length is accepted if it

passes the address filtering or if the RXALL bit is set. The Pass Bad Frames (PASSBAD) bit in the Receive Con-

figuration Register (RX_CFG) determines if the Packet Filter bit in the RX Status is set (PASSBAD=1) or cleared

(PASSBAD=0). The Filtering Fail bit will indicate if the address filtering passed or failed.

• A frame that has an error (runt, collision, CRC) and is 60 bytes or under in length is accepted if it passes the

address filtering or if the RXALL bit is set and the Pass Bad Frames (PASSBAD) bit is set. The Packet Filter bit in

the RX Status is set for these frames. The Filtering Fail bit will indicate if the address filtering passed or failed.

11.6

Wake-On-LAN (WOL)

The following bits of the Host MAC Wake-up Control and Status Register (HMAC_WUCSR), when enabled, may allow

a WOL event to be asserted:

• Perfect DA Wakeup Enable (PFDA_EN)

• Broadcast Wakeup Enable (BCST_EN)

• Wake-Up Frame Enable (WUEN)

• Magic Packet Enable (MPEN)

The WoL Wait for Sleep (WOL_WAIT_SLEEP) bit in Host MAC Wake-up Control and Status Register (HMAC_WUCSR)

will delay the WoL functions until the host has put the device into a power down mode.

WOL events may be indicated to the power management block via the Wake On Status (WOL_STS) bit of the Power

Management Control Register (PMT_CTRL). Each WOL event type is detailed in the following sub-sections.

The WoL feature is part of the broader power management features of the device and can be used to trigger the power

management event output pin (PME) or general interrupt request pin (IRQ). This is accomplished by enabling the

desired WoL feature and setting the Wake-On-Enable (WOL_EN) bit of the Power Management Control Register

(PMT_CTRL). Refer to Section 6.3, "Power Management," on page 44 for additional information.

11.6.1

PERFECT DA DETECTION

Setting the Perfect DA Wakeup Enable (PFDA_EN) bit in the Host MAC Wake-up Control and Status Register

(HMAC_WUCSR) places the MAC in the Perfect DA detection mode. In this mode, normal data reception is disabled,

and detection logic within the MAC examines the destination address of each received frame.

When a frame whose destination address matches that specified by the Host MAC Address High Register (HMAC_AD-

DRH) and Host MAC Address Low Register (HMAC_ADDRL) is received, the Perfect DA Frame Received (PFDA_FR)

bit in the Host MAC Wake-up Control and Status Register (HMAC_WUCSR) is set. When the host clears the PFDA_EN

bit, the Host MAC will resume normal receive operation.

LAN9250 датащи(PDF) 144 Page - Microchip Technology

LAN9250 датащи(HTML) 144 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL