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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM32F413XG датащи(PDF) 155 Page - STMicroelectronics |
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STM32F413XG датащи(HTML) 155 Page - STMicroelectronics |
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155 / 207 page  DocID029162 Rev 2 155/207 STM32F413xG/H Electrical characteristics 174 6.3.25 DFSDM characteristics Unless otherwise specified, the parameters given in Table 86 for DFSDM are derived from tests performed under the ambient temperature, fAPB2 frequency and VDD supply voltage conditions summarized in Table 16: General operating conditions. • Output speed is set to OSPEEDRy[1:0] = 10 • Capacitive load C = 30 pF • Measurement points are done at CMOS levels: 0.5 * VDD Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function characteristics (DFSDM_CKINy, DFSDM_DATINy, DFSDM_CKOUT for DFSDM). Table 86. DFSDM characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fDFSDMCLK DFSDM clock 1.71 < VDD < 3.6 V - - fSYSCLK MHz fCKIN (1/TCKIN) Input clock frequency SPI mode (SITP[1:0] = 0,1), External clock mode (SPICKSEL[1:0] = 0, 1.71 < VDD < 3.6 V -- 20 (fDFBDMCLK / 4 SPI mode (SITP[1:0] = 0,1), External clock mode (SPICKSEL[1:0] = 0, 2.7 < VDD < 3.6 V -- 20 (fDFBDMCLK / 4 SPI mode (SITP[1:0] = 0,1), Internal clock mode (SPICKSEL[1:0] ≠ 0, 1.71 < VDD < 3.6 V -- 20 (fDFBDMCLK / 4 SPI mode (SITP[1:0] = 0,1), Internal clock mode (SPICKSEL[1:0] ≠ 0, 2.7 < VDD < 3.6 V -- 20 (fDFBDMCLK / 4 fCKOUT Output clock frequency 1.71 < VDD < 3.6 V - - 20 DuCyCKOUT Output clock frequency duty cycle 1.71 < VDD < 3.6 V 45 50 55 % |
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