SAP5SD-A-G1-R datasheet(15/66 Pages) IDT

15 / 66 page

SAP51 / SAP5S Datasheet

January 28, 2016

The data port is accompanied by the data strobe signal DSTBn. There is a defined phase relation between a data

output event, the input data sampling and the activation of the DSTBn signal. Thus, it can be used to trigger

external logic or a microcontroller to process the received data or to provide new input data for the AS-i slave

response. See section 5.8 for further details.

3.2.5.

Data Input Inversion

By default, the logic signal (HIGH/LOW) that is present at the data input pins during the input sampling phase is

transferred without modification to the send register, which is interfaced by the UART. Thus, the signal becomes

directly part of the slave response.

Some applications work with inverted logic levels. To avoid additional external inverters, the input signal can be

inverted by the SAP5 before transferring it to the send register. The inversion of the input signals can be done

jointly for all data input pins. See section 5.8.

3.2.6.

Data Input Filtering

To prevent input signal bouncing from being transferred to the AS-i master, the data input signals can be digitally

filtered. Activation of the filter is done jointly either by EEPROM configuration or by the logic state of parameter

port pin P2. For more detailed information, refer to section 5.8.

3.2.7.

Synchronous Data I/O Mode

AS-Interface Complete Specification V3.0 newly defines a synchronous data I/O feature, which allows a number

of slaves in the network to switch their outputs at the same time and to have their inputs sampled simultaneously.

This feature is especially useful if more than 4-bit wide data is to be provided synchronously to an application.

The synchronization point is defined as the data exchange event of the slave with the lowest address in the

network. This definition relies on the cyclical slave polling with increasing slave addresses per cycle, which is one

of the basic communication principles of AS-i. The SAP5 always monitors the data communication and detects

the change from a higher to a lower slave address. If such a change has been recognized, the SAP5 assumes

that the slave with the lower address has the lowest address in the network.

There are some special procedures that become active during the start of synchronous I/O mode operation and if

more than three consecutive telegrams have been sent to the same slave address. This is described in more

detail in section 5.8.3.

3.2.8.

4 Input / 4 Output Processing in Extended Address Mode

A new feature of AS-Interface Complete Specification V3.0 is additional support of 4-bit wide output data in

Extended Address Mode. Until AS-Interface Complete Specification V2.11, it was only possible to send three data

output bits from the master to the slave in Extended Address Mode because telegram bit I3 was used to select

between the A or B slave type for extended slave addressing (up to 62 slaves per network). In normal address

mode, bit I3 carries output data for pin D3.

SAP5SD-A-G1-R датащи(PDF) 15 Page - Integrated Device Technology