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SAP5SD-A-G1-R датащи(PDF) 51 Page - Integrated Device Technology

номер детали SAP5SD-A-G1-R
подробное описание детали  AS-Interface Spec. V3.0 Compliant Universal AS-i IC
PDF  66 Pages
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производитель  IDT [Integrated Device Technology]
домашняя страница  http://www.idt.com
Logo IDT - Integrated Device Technology

SAP5SD-A-G1-R датащи(HTML) 51 Page - Integrated Device Technology

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SAP51 / SAP5S Datasheet
© 2016 Integrated Device Technology, Inc.
51
January 28, 2016
Table 5.24 Activation of the SAP5 Master/Repeater Mode
Master_Mode
EEPROM flag
ID_Code
Master Mode 1
Master Mode 2
Repeater Mode
0
x
OFF
OFF
OFF
1
0 to 4
ON
OFF
OFF
1
6 to FHEX
OFF
ON
OFF
1
5
OFF
OFF
ON
5.19.2. Pin Assignment in Master and Repeater Modes
In Master and Repeater Mode, the SAP5 pins are configured as follows. Pins that are not used are kept at logic
high (high impedance) state in order to reduce internal power dissipation of the SAP5.
Figure 5.9
SAP Package Pin Assignment in Master/Repeater Mode
RESETn
RX_DAT
OSC2
OSC1
not used
not used
not used
TX_DAT
not used
not used
not used
not used
APF
not used
not used
UOUT
U5R
LTGN
CDC
LTGP
SAP5
Pin 1
Table 5.25 SAP5 Pin Assignment in Master and Repeater Modes
SOP 20
Pin #
SOP 16
Pin #
Name
Signal Name
Pin Configuration
Description
in Master/Repeater Mode
1
-
P1
None
I/O
Not used
2
-
P0
None
I/O
Not used
3
1
D1
None
I/O
Not used
4
2
D0
TX_DAT
IN
Transmit signal (Manchester II signal)
5
3
DSTBn
RESETn
IN
External reset input (active LOW)
6
4
LED1
RX_DAT
OUT
Receive signal (Manchester II signal)
7
5
OSC2
OSC2
OUT
Crystal oscillator



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