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DS20005550A-page 7

HV9901

2.0

PIN DESCRIPTION

The pin details of HV9901 are listed on Table 2-1. See

Package Type for the location of the pins.

TABLE 2-1:

PIN TABLE

Pin Number

Pin Name

Description

1

VIN

Input supply

2

—

Pin not present

3

—

Pin not present

4

GT

Gate driver output for driving the external switching MOSFET

5

CS

Current sense input

6

GND

Ground

7

SYNC

Open-drain input/output for synchronizing the internal PWM oscil-

lator to other HV9901s or to an external clock

8

RT

A resistor from this pin to ground sets the PWM switching fre-

quency.

9

POL

Input that determines the polarity of the ENI input.

See Truth Table.

10

ENO

Enable output. It is the logical inversion of the ENI signal.

11

ENI

Enable input. Whether ENI is active low or active high is deter-

mined by the POL input.

12

VCC

Output of the auxiliary regulator. Output voltage is determined by

the resistive divider connected to the FB pin.

13

FB

Feedback input for the auxiliary regulator.

14

H/D

HOLD/DELAY input. An RC network connected to this pin controls

the pull-in time and the holding current. See equations on page 4.

15

VREF

Reference voltage. Bypass locally with a 10 nF capacitor.

16

VDD

Output of the internal supply regulator. Bypass locally with a 10 nF

capacitor.