FLASH

AS8FLC2M32

AS8FLC2M32B

Rev. 1.6 05/11

Micross Components reserves the right to change products or specifications without notice.

2

The device requires only a single 3.3volt power supply for

both READ and WRITE operations. Internally generated and

regulated voltages are provided for the program and erase

functions.

The device is entirely command set compatible with the

JEDEC SINGLE POWER FLASH STANDARD. Com-

mands are written to the command register using standard

microprocessor write timings. Register contents serve as

input to an internal state-machine that controls the erase and

programming circuitry. Write cycles also internally latch

addresses and data required for the programming or erase

function(s). Reading data out of the array is similar to reading

from other electrically programmable devices.

Device programming occurs by executing the program

command sequence.

This initiates the EMBEDDED

PROGRAM algorithm that automatically times the WRITE

PULSE widths and cycle and verifies each cell for proper

cell margins. The UNLOCK BYPASS mode facilitates faster

programming times by requiring only two WRITE cycles to

program data instead of four.

Device erasure occurs by executing the erase command

sequence. This initiates the Embedded Erase algorithm, an

internal algorithm that automatically pre-programs the array

before executing the erase operation. During erasure, the

device automatically times the erase pulse widths and verifies

proper cell margin.

The host system can detect whether a program or erase

operation is complete by reading the DQ7 (Data\ Polling) and

DQ6 (toggle) STATUS BITS. After a program or erase cycle

has been completed, the device is ready to read array data or

accept another command.

The SECTOR ERASE ARCHITECTURE allows memory

sectors to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully erased when

shipped from Micross.

Hardware data protection measures include a low VCC

detector that automatically inhibits WRITE operations during

power transitions. The hardware sector protection features

disables both program and erase operation in any combination

of the sectors of memory. This can be achieved in-system or

via specially adapted commercial programming equipment.

The ERASE SUSPEND feature enables the user to put erase

on hold for any period of time to read data from, or program

data to, any sector which is not selected for erasure. True

BACKGROUND ERASE can thus be achieved.

The HARDWARE RESET\ PIN terminates any operation

in progress and resets the internal state machine to a READ

operation. The RESET\ pin may be tied to the system reset

circuitry.

LOGIC DIAGRAM (Byte)

1M x 8

1M x 8

1M x 8

1M x 8

RESET\

OE\

A0-Ax

WE1\

WE2\

WE3\

WE4\

CS1\

CS2\

CS3\

CS4\

BLOCK DIAGRAM

I/O0-7

I/O8-15

I/O16-23

I/O24-31

68-Ld. CQFP, Package "QT"

1M x 8

1M x 8

1M x 8

1M x 8

RESET\

OE\

A0-Ax

WE\

CS1\

CS2\

CS3\

CS4\

BLOCK DIAGRAM

I/O0-7

I/O8-15

I/O16-23

I/O24-31

66-Ld. HIP, Package "H"

P

2

2

2

2

2

2

2

2

DQ

DQ

DQ

DQ

DQ

DQ

DQ

DQ

DQ

GND

VCC

RESET\

WEx\

RY/BY\

CSx\

X-Decoder

DQ (byte)

OE\

A0-Ax

Y-Decoder

State

Control

Command

Register

VCC Detector

Timer

PGM Voltage

Generator

Chip Enable

Output Enable

Logic

Y-Gating

Cell Matrix

I/O Buffers

Data Latch

Erase Voltage

Generator

Sector

Switches