Application information

TSU111

18/30

DocID029790 Rev 2

5.2

Rail-to-rail input

The TSU111 is built with two complementary PMOS and NMOS input differential pairs.

Thus, the device has a rail-to-rail input, and the input common mode range is extended

The TSU111 has been designed to prevent phase reversal behavior.

5.3

Input offset voltage drift over temperature

The maximum input voltage drift variation over temperature is defined as the offset

variation related to the offset value measured at 25 °C. The operational amplifier is one of

the main circuits of the signal conditioning chain, and the amplifier input offset is a major

contributor to the chain accuracy. The signal chain accuracy at 25 °C can be compensated

during production at application level. The maximum input voltage drift over temperature

enables the system designer to anticipate the effect of temperature variations.

The maximum input voltage drift over temperature is computed using Equation 1.

Equation 1

Where T = -40 °C and 85 °C.

The TSU111 datasheet maximum values are guaranteed by measurements on a

5.4

Long term input offset voltage drift

To evaluate product reliability, two types of stress acceleration are used:

Voltage acceleration, by changing the applied voltage

Temperature acceleration, by changing the die temperature (below the maximum

junction temperature allowed by the technology) with the ambient temperature.

The voltage acceleration has been defined based on JEDEC results, and is defined using

Equation 2.

Equation 2

Where:

β is the voltage acceleration constant in 1/V, constant technology parameter (β = 1)

The temperature acceleration is driven by the Arrhenius model, and is defined in

Equation 3.

∆V

io

∆T

ma x

V

V

–

T

25 °C

–

=

°C

A

FV

e

β V

S

V

U

–

.

=