PL138-48

DS20005543B-page 10

 2016 Microchip Technology Inc.

5.0

APPLICATION INFORMATION

5.1

Input Logic Configurations

The following circuits show different configurations for different input logic type signals. For good signal integrity at the

PL138 input, the signals need to be properly terminated according to the logic type requirements. The signals need to

FIGURE 5-1:

CLK-IN Input Driven by a

3.3V LVPECL Driver.

FIGURE 5-2:

3.3V LVPECL Driver,

Alternative Termination.

FIGURE 5-3:

CLK-IN Input Driven by a

CML Driver.

FIGURE 5-4:

CLK-IN Input Driven by an

SSTL Driver.

FIGURE 5-5:

CLK-IN Input Driven by an

LVDS Driver.

FIGURE 5-6:

LVDS Driver, Alternative

AC-Coupling.

This circuit is for compatibility only. AC-coupling is not

reaches low enough that LVDS signals can be

connected directly to the PL138 input like in the circuit

in Figure 5-5.

FIGURE 5-7:

CLK-IN Input Driven by a

CMOS Driver.