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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STLUX385ATR датащи(PDF) 43 Page - STMicroelectronics |
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STLUX385ATR датащи(HTML) 43 Page - STMicroelectronics |
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43 / 126 page  DocID027870 Rev 1 43/126 STLUX I/O multifunction signal configuration 126 Bit 7 - 6: RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations. MSC_IOMXP2 (Port P2 I/O MUX control register) The Port1 I/O multifunction signal configurations register (for functionality description refer to Section 7.5). This register is not available on STLUX285A and must be kept set to its default value Check device feature availability. Bit 3 - 0: RFU reserved; must be kept 0 during register writing for future compatibility Bit 4: Sel_P254 Port2 [5:4] I/O multiplexing scheme: 0: Port2 [5:4] are interconnected to I2C_scl and I2C_sda signals 1: Port2 [5:4] are interconnected to DIGIN [5:4] signals Bit 6 - 5: RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0 during register write operations. Bit 7: Sel_SWIM SWIM alternate function signal enable; this feature is active when the SWD field of the register CFG_GCR is set. 0: SWIM pin is configured with GPIO0 [6] signal. 1: SWIM functionality is preserved. Table 11. MSC_IOMXP2 (Port P2 I/O MUX control register) Offset: 0x13 (indirect area) Default value: 0xFF 76 5432 1 0 Sel_SWIM RFU Sel_P254 RFU r/w r r/w r |
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