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STLUX385ATR датащи(PDF) 101 Page - STMicroelectronics |
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STLUX385ATR датащи(HTML) 101 Page - STMicroelectronics |
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101 / 126 page ![]() DocID027870 Rev 1 101/126 STLUX Electrical characteristics 126 12.3.6 I/O port pin characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. Unused input pins should not be left floating. Table 83. Voltage DC characteristics Symbol Description Min.(1) 1. Data based on characterization result, not tested in production. Typ. Max.(1) Unit VIL Input low voltage -0.3 0.3 * VDD V VIH Input high voltage(2) 2. All signals are not 5 V tolerant (input signals can't be exceeded VDDX (VDDX = VDD, VDDA). 0.7 * VDD VDD VOL1 Output low voltage at 3.3 V(3), (4) 3. A high sink selectable by high speed configuration; the parameter applicable to signals: GPIO0 [5:0] (product depending). 4. The parameter applicable to signals: GPIO1 [5:0]/PWM [5:0] (product depending). 0.4(5) 5. Electrical threshold voltage not yet characterized at -40 ºC. VOL2 Output low voltage at 5 V(3), (4) 0.5 VOL3 Output low voltage high sink at 3.3 V / 5 V(2),(6), (7) 6. The parameter applicable to the signal: SWIM. 7. The parameter applicable to the signal: DIGIN [0]/CCO_clk. 0.6(5) VOH1 Output high voltage at 3.3 V(3), (4) VDD - 0.4(5) VOH2 Output high voltage at 5 V(3), (4) VDD - 0.5 VOH3 Output high voltage high sink at 3.3 V / 5 V(2), (6), (7) VDD - 0.6(5) HVS Hysteresis input voltage(8) 8. Applicable to any digital inputs. 0.1 * VDD RPU Pull-up resistor 30 45 60 k |
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