OV7620 datasheet(47/60 Pages) ETC

47 / 60 page

OV7620 Product Specifications - Rev. 1.2 (5/13/00)

OMNIVISION TECHNOLOGIES INC.

Preliminary Company Confidential

COMK7 - “1” HREF edges coincident (no delay) with PCLK negative/falling edges (COMD6 must be set to

“0”). “0” HREF edge occurs 10 ns after PCLK positive/rising edge.

COMK6 - Output port drive current additional 2x control bit.

COMK5 - Reserved.

COMK4 - Selects ZV port timing. “1” VSYNC output ZV port vertical sync signal. “0” normal TV vertical

sync signal.

COMK3 - Accelerated saturation mode for camera mode change. (QVGA, 8 Bit output, CCIR 656 mode

and Progressive Scan Mode). After relative control bit set, the first VS will be the stable image

with suitable AEC/AWB setting. “0” - slow mode, after mode change need more field/frame to

get stable AEC/AWB setting image.

COMK2 - Reserved.

COMK1 - AWB update rate selection. “1” fast mode; “0” slow mode.

COMK0 - Set to “1” in single line mode, otherwise set to “0” and set COMG4 to disable.

COML7 - Auto Brightness update rate: “1” - Slow mode; “0” - fast mode.

COML6 - Gated PCLK selection. “1” - Enables PCLK gated by HREF; “0” - PCLK is free running clock

COML5 - Swap HREF output pin with CHSYNC. “1” - HREF pin output CHSYNC signal; “0” - No swap.

COML4 - Swap CHSYNC output pin with HREF. “1” - CHSYNC pin output HREF signal; “0” - normal out-

put.

COML<3:2>- Highest 2 bit for HSYNC rising edge shift control, combined with register [72]

COML<1:0>- Highest 2 bit for HSYNC falling edge shift control, combined with register [73]

HSDY<7:0> - Lower 8 bit control for shifting horizontal sync CHSYNC first edge. Range is [000] - [3FF].

Every count equals 1 PCLK.

Bits

COMK7

COMK6

COMK5

COMK4

COMK3

COMK2

COMK1

COMK0

Default

Bits

COML7

COML6

COML5

COML4

COML3

COMK2

COML1

COML0

Default

Bits

HSDY7

HSDY6

HSDy5

HSDY4

HSDY3

HSDY2

HSDY1

HSDY0

Default

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