CS89712 datasheet(109/170 Pages) CIRRUS

109 / 170 page

CS89712

DS502PP2

109

3.16.1.6

Right Channel Receive FIFO Interrupt Mask (RCRM)

The Right Channel Receive FIFO interrupt mask (RCRM) bit is used to mask or enable the Right

Channel Receive FIFO service request interrupt. When RCRM = 0, the interrupt is masked and the

state of the Right Channel Receive FIFO service request (RCRS) bit within the DAI status register is

ignored by the interrupt controller. When RCRM = 1, the interrupt is enabled, and whenever RCRS is

set (one), an interrupt request is made to the interrupt controller. Note that programming RCRM = 0

does not affect the current state of RCRS or the Right Channel Receive FIFO logic’s ability to set and

clear RCRS, for it only blocks the generation of the interrupt request.

3.16.2

DAI Data Registers

The DAI contains three data registers: DAIDR0 addresses the top entry of the Right Channel Transmit

FIFO and bottom entry of the Right Channel Receive FIFO; DAIDR1 addresses the top and bottom entry

of the Left Channel Transmit and Receive FIFOs, respectively; and DAIDR2 is used to perform enable and

disable the DAI FIFOs.

3.16.3

DAIDR0 DAI Data Register 0 (address 0x8000.2040)

When DAI Data Register 0 (DAIDR0) is read, the bottom entry of the Right Channel Receive FIFO is

accessed. As data is removed by the DAI’s receive logic from the incoming data frame, it is placed

into the top entry of the Right Channel Receive FIFO and is transferred down an entry at a time until

it reaches the last empty location within the FIFO. Data is removed by reading DAIDR0, which ac-

cesses the bottom entry of the right channel FIFO. After DAIDR0 is read, the bottom entry is invali-

dated, and all remaining values within the FIFO automatically transfer down one location.

When DAIDR0 is written, the top-most entry of the Right Channel Transmit FIFO is accessed. After a

write, data is automatically transferred down to the lowest location within the transmit FIFO which

does not already contain valid data. Data is removed from the bottom of the FIFO one value at a time

by the transmit logic, loaded into the correct position within the 64-bit transmit serial shifter, then se-

rially shifted out onto the SDOUT pin.

Table 59 shows DAIDR0. Note that the Transmit and Receive Right Channel FIFOs are cleared when

the device is reset, or by writing a zero to DAIEN (DAI disabled). Also, note that writes to reserved

bits are ignored and reads return zeros.

31-16

15-0

Reserved

Bottom of Right Channel Receive FIFO

Read Access

31-16

15-0

Reserved

Top of Right Channel Transmit FIFO

Write Access

Bit

Description

0-15

RIGHT CHANNEL DATA: Transmit / Receive Right Channel FIFO Data

Read — Bottom of Right Channel Receive FIFO data

Write — Top of Right Channel Transmit FIFO data

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