GC5016 datasheet(77/88 Pages) TI

77 / 88 page

GC5016

SLWS142G − JANUARY 2003 − REVISED NOVEMBER 2005

www.ti.com

17.16 CIC and MIXER Control Registers

There are two cicmix blocks. The blocks are arranged as channel AB and channel CD:

page 0x80, addresses 0x10−0x17

channel A,

page 0x80, addresses 0x18 to 0x1F

channel B,

page 0xA0, addresses 0x10−0x17

channel C,

page 0xA0, addresses 0x18 to 0x1F

channel D.

Table 52 and 59 lists the CIC controls. The cic_shift, cic_rshift, cic_rcv_full, are the cic gain controls. The cic_rcv,

cic_xmt_5stg, cic_2x, cic_xmt_d6stg, and cic_bypass are the mode controls. The cic_rcv_cross is used to select

the DDC input for the dual CIC in channels B and D.

Table 53, 54, 55, and 56 set the frequency register (delta phase) and phase (initial phase) values.

Table 57 is the mixer configuration, this sets the I and Q data source, and the cosine and sine multiplier selections.

Table 58 is the mixer synchronization register.

Table 52. CIC Mode Page 0x80 Address 0x10

Rcv

FIELD

BITS

Dflt

DESCRIPTION

cic_shift

5..0

CIC is followed by a shifter by a shifter to compensate for CIC gain. 0

≤ cic_shift ≤ 39.

cic_rcv

7..6

CIC mode is quiet (0), receive (1), transmit (2), or illegal (3)

cic_xmt_5stg

CIC transmits five stages (1), rather than the normal six stages (0)

cic_rshift

Upshift 1 bit in receive mode after CIC filtering before rounding

cic_2x

Operate the CIC in double rate mode

cic_xmt_d6stg

Must be set for CIC in double rate and six stage, else clear

cic_rcv_cross

Use cross-strapped CIC inputs in receive. Set for splitiq mode

cic_rcv_full

Saturate CIC output at full scale (1) for nonsymmetrical FIR or half scale (0) for symmetric

FIR. Only affects receive outputs.

cic_bypass

Bypass CIC in transmit (1), must also set cic_shift (39) and ncic (0). Clear in receive.

−

cic_fl_status

CIC flush status sticky bit. Chip sets if autoflushed. User must clear.

Table 53. Phase Page 0x80 Address 0x11

Rcv

FIELD

BITS

Dflt

DESCRIPTION

phase

15..0

Phase is phase/216 Hz

Table 54. Frequency (LSB) Page 0x80 Address 0x12

Rcv

FIELD

BITS

Dflt

DESCRIPTION

freq_lsb

15..0

Bottom 16 bits of frequency

Table 55. Frequency (mid) Page 0x80 Address 0x13

Rcv

FIELD

BITS

Dflt

DESCRIPTION

freq_mid

15..0

Middle 16 bits of frequency

Table 56. Frequency (MSB) Page 0x80 Address 0x14

Rcv

FIELD

BITS

Dflt

DESCRIPTION

freq_msb

15..0

Top 16 bits of frequency. Values in Table 54 through Table 56 may be set using the pseudo

field freq.

GC5016 датащи(PDF) 77 Page - Texas Instruments

GC5016 датащи(HTML) 77 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

датащи скачать

ссылки URL