GC2011A datasheet(20/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

3.3

QUARTER RATE

The number of taps in the filter can be quadrupled if the data rate into and out of the chip is one quarter the

clock rate. In this mode each filter cell stores four filter coefficients and performs two tap multiplications per output

sample. The cells’ delay lines are adjusted so that four feed-forward and four feedback data samples are delayed within

each filter cell. The accumulator at the end of the filter path sums the products to give the quarter rate output. The chip

is configured in the quarter rate mode using the control settings shown in Table 4.

The coefficients are stored in the filter cells using the formula:

Store h(k) in memory address BASE+k.

where BASE is 128 for A-path or cascaded filters and is 192 for B-path filters.

All four coefficients are active within each filter cell so the user can not switch between banks of filter

coefficients. To change or update the coefficients in the quarter rate mode, the user should set the SYNC_COEF control

bit. When set, this bit synchronizes the control write operation to the data clock in order to prevent any filter transients

or “glitches” due to asynchronous coefficient changes. This allows single coefficients to be updated synchronously

3.4

DOUBLE RATE I/O

The chip will filter data samples which are received at twice the clock rate. The user must split the data into

two data streams, each at the clock rate, one containing even time samples and one containing odd time samples. The

even data stream is then used as the A-in input and the odd data stream is used as the B-in input. Two chips are required

to perform the filtering, one for the even time outputs and one for the odd time outputs. The filtered samples are output

on the A-out pins of each chip. If the filter is intended to be a decimate by two filter, then only one chip is needed since

only the even time output samples need be generated. The double rate mode control register settings are shown in

Table 5.

The filter coefficients h(k) are stored in addresses:

128+2*k+1

for k even, and

192+2*k-1

for k odd,

where k ranges from 0 to 31. h(31) is the center tap for the odd symmetry filters.

Table 4: Quarter Rate Mode Control Register Settings

Symmetry

Dual Path or

Cascaded

# of Taps

(N)

A-PATH

B-PATH

Cascade

Latency

REG0

REG1

REG0

REG1

REG

None

Dual

A202

8E00

8202

8E00

2000

Cascaded

128

A202

8E28

8202

8E00

5E00

Even

Dual

128

A202

9018

8202

9018

2000

Cascaded

256

A202

9028

8202

9018

5E00

Odd

Dual

127

A202

9094

8202

9094

2000

Cascaded

255

A202

90A8

8202

9094

5E00

Table 5: Double Rate Mode Control Register Settings

Output

Symmetr

# of Taps

(N)

A-PATH

B-PATH

Cascade Output

Latency

REG0 REG1 REG0 REG1

REG

Even Output chip

None

60d8

6000

00D8

6000

2000

0048

Odd

60d8

6108

00D8

6181

2000

0048

Odd Output chip

None

00d8

6000

20D8

6000

2000

0048

Odd

00d8

6108

20D8

6181

2000

0048

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