GC2011A datasheet(14/50 Pages) TI

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Texas Instruments Incorporated

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GC2011A 3.3V DIGITAL FILTER CHIP

SLWS129A

This document contains information which may be changed at any time without notice

delayed by four cycles. In the interpolate modes the samples are held for multiple clock cycles rather than delayed.

Details of the delay control modes are described in Section 6.1

The 12 bit adder can operate in the signed or unsigned mode. In the signed mode it outputs a 13 bit result

which is sign extended to 14 bits. In the unsigned mode it outputs a 14 bit signed result, where the 14th bit (the sign bit)

is forced to zero. The 14 bit adder output is multiplied by a 14 bit coefficient selected by the C-Sel control from one of

four 16 bit coefficient registers. The 14 bit coefficient is taken from the 14 LSBs of the 16 bit registers.

A 32 bit adder adds the 28 bit multiplier output to the 32 bit sum in data and outputs the result to the next filter

cell.

2.8

ACCUMULATOR

The sum output from the filter path is passed to a 32 bit accumulator as shown in Figure 1. The accumulator

can be programmed to accumulate blocks of 1, 2 or 4 samples. The accumulator is used to expand the effective length

of the filter when the output rate is less than the clock rate. Modes that use the accumulator are the decimation, half

rate, and quarter rate modes.

2.9

24 BIT MUX CIRCUIT

The 24 bit mux circuit is used when filtering 24 bit input data. To use this mode the user splits the 24 bit input

data into the upper 12 bits and the lower 12 bits. The upper 12 bits are used as the A-path input and the lower 12 bits

are used as the B-path input. The two paths are programmed the same except that the A-path is configured for signed

inputs and the B-path is configured for unsigned inputs. The same filter coefficients are loaded into the two paths. The

sum outputs from the two paths are then added together by shifting the B-path sum down by 12 bits, rounding the result

(using the round-to-even algorithm), and adding it to the A-path output. The 32 bit result is passed through the gain

circuit, rounded to 24 bits and output on the A and B output pins. The upper 16 bits of the result are output on the A-out

pins and the lower 8 bits are output on the upper 8 bits of the B-out pins.

2.10

SUMMER

The summer circuit is used to add the results from the two paths together. This feature is used in the 24 bit

input mode, the double rate modes, and when implementing complex filters. The adder can be converted to a subtracter

by using the input negation controls.

IMPORTANT

The 32 bit accumulator does not guard against overflow. It is the user’s respon-

sibility to insure that the filter’s gain will not cause overflow. Overflow will not

occur if the user restricts the filter coefficients so that the sum of their absolute

values is less than 220. Since the maximum absolute value of any 14 bit coeffi-

cient is 213, this restriction does not affect filters with less than 128 taps. For

those filters with lengths greater than 128 taps, which are found in the decimate

by 4 and quarter rate modes, this restriction only applies to the hypothetical

case where every coefficient is close to full scale.

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