TFP501

PanelBus

 HDCP DIGITAL RECEIVER

SLDS127B – JULY 2001 – REVISED AUGUST 2002

13

POST OFFICE BOX 655303

high-bandwidth digital content protection (HDCP) overview (continued)

The HDCP keys must also be protected from access. TI has chosen to avoid the inconvenience and possible

circuit board damage from using epoxy or other barriers between the EEPROM and DVI receiver. An encryption

scheme is used to protect the HDCP device key values passing from an off-chip EEPROM to the HDCP receiver

EEPROM, decrypted, and used to enable HDCP functionality. TI’s HDCP solution provides real advantages with

respect to lower systems level cost, ease of implementation, high performance, and exceptional security.

S/W

Application

Program

Upstream

Decrypt

CPU

and

North

Bridge

and

Graphics

Controller

TFP510

DVI-HDCP TX

(PC’s DVI Output)

PROM

Key

Decrypt

C Keys and KSV

Upstream

Encrypt

DE

Pixel Data

Clock

Input

Stream

Encrypted Keys

A Keys and KSV

D Keys and KSV

I2C

Encrypted M0

I2C

TFP501

DVI-HDCP RX

(Display’s DVI Input)

PROM

Key

Decrypt

I2C

Slave I/F

Channel 2

Channel 0

Channel C

HDCP Encrypted

TMDS Link

Encrypted Keys

B Keys and KSV

I2C

I2C

Channel 1

EDID

PROM

Control and Authentication and Key Exchange

KSV = Key Selection Vector

M0 = 64-Bit Secret Value

DE

Pixel Data

Clock

Output

Stream

Figure 13. TI’s HDCP Implementation for PC and Display System

TFP501 clocking and data synchronization

The TFP501 receives a clock reference from the DVI transmitter, such as the TFP510, that has a period equal

encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the

pixel rate. For example, the required pixel rate to support an UXGA resolution with 60 Hz refresh rate is

165 MHz. The T.M.D.S. serial bit rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high speed

digital bit stream on three separate channels (or twisted-pair wires) of long distances (3–5 meters), phase

synchronization between the data steams and the input reference clock is not assured. In addition, skew

between the three data channels is common. The TFP501 uses a 4x oversampling scheme of the input data

Accumulated jitter on the clock and data lines due to reflections and external noise sources is also typical of

high-speed serial data transmission. The TFP501 is designed for high jitter tolerance.