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MIC2126 датащи(PDF) 25 Page - Microchip Technology

номер детали MIC2126
подробное описание детали  28V Synchronous Buck Controllers Featuring Adaptive ON-Time Control
PDF  34 Pages
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производитель  MICROCHIP [Microchip Technology]
домашняя страница  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MIC2126 датащи(HTML) 25 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS20005459B-page 25
MIC2125/6
6.0
PCB LAYOUT GUIDELINES
PCB layout is critical to achieve reliable, stable and
efficient performance. The following guidelines should
be followed to ensure proper operation of the
MIC2125/26 converter.
6.1
IC
• The ceramic bypass capacitors which are
connected to the VDD and PVDD pins must be
located right at the IC. Use wide traces to connect
to the VDD, PVDD and AGND, PGND pins
respectively.
• The signal ground pin (AGND) must be connected
directly to the ground planes.
• Place the IC close to the point-of-load (POL).
• Signal and power grounds should be kept
separate and connected at only one location.
6.2
Input Capacitor
• Place the input ceramic capacitors as close as
possible to the MOSFETs.
• Place several vias to the ground plane close to
the input capacitor ground terminal.
6.3
Inductor
• Keep the inductor connection to the switch node
(SW) short.
• Do not route any digital lines underneath or close
to the inductor.
• Keep the switch node (SW) away from the
feedback (FB) pin.
• The SW pin should be connected directly to the
drain of the low-side MOSFET to accurately
sense the voltage across the low-side MOSFET.
6.4
Output Capacitor
• Use a copper plane to connect the output
capacitor ground terminal to the input capacitor
ground terminal.
• The feedback trace should be separate from the
power trace and connected as close as possible
to the output capacitor. Sensing a long
high-current load trace can degrade the DC load
regulation.
6.5
MOSFETs
• MOSFET gate drive traces must be short. The
ground plane should be the connection between
the MOSFET source and PGND.
• Choose a low-side MOSFET with a high CGS/CGD
ratio and a low internal gate resistance to
minimize the effect of dv/dt inducted turn-on.
• Use a 4.5V VGS rated MOSFET. Its higher gate
threshold voltage is more immune to glitches than
a 2.5V or 3.3V rated MOSFET.
For more information about the Evaluation board layout, please contact Microchip sales.



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