FEDL620Q150A-01

ML620Q151A/2A/3A/4A/5A/6A/7A/8A/9A

3/36

• General-purpose ports （including secondary functions）

− Input-only ports

Input-only ports (including multiple

functions)

Product

When not using the

crystal resonator

When

using

the

crystal resonator

ML620Q151A/ML620Q152A/ML620Q153A

6ch

5ch

ML620Q154A/ML620Q155A/ML620Q156A

7ch

6ch

ML620Q157A/ML620Q158A/ML620Q159A

7ch

6ch

− Output-only ports : 4ch

− Input/output ports

Input/output ports (including multiple

functions)

Product

When not using the

crystal resonator

When

using

the

crystal resonator

ML620Q151A/ML620Q152A/ML620Q153A

31ch

30ch

ML620Q154A/ML620Q155A/ML620Q156A

34ch

33ch

ML620Q157A/ML620Q158A/ML620Q159A

46ch

45ch

• Reset

− Reset through the RESET_N pin

− Power-on reset generation when powered on

− Reset by the watchdog timer (WDT) overflow

− Reset by the Low Level Detector (LLD)

• Low Level detect function

− Threshold voltages: 4values (1.9V/2.55V/3.7V/4.2V)

A threshold voltage is selected as Code-Option.

− LLD is a ready as a supply-voltage supervisory reset.

Reset or an interrupt output is selectable as Code-Option.

• Clock

− Low-speed clock (This LSI can not guarantee the operation without low-speed clock)

Crystal oscillation (32.768 kHz) or Built-in RC oscillation (32.768kHz)

Crystal oscillation or Built-in RC oscillation is selectable as Code-Option.

− High-speed clock

Built-in RC oscillation (2.097MHz) or Built-in PLL oscillation (8.192MHz)

• Power management

− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).

− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are

stopped.)

− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation

clock)

− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop)