ML610Q421 datasheet(31/37 Pages) LAPIS

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FEDL610Q421-03

ML610Q421/ML610Q422

AC CHARACTERISTICS (Synchronous Serial Port)

(VDD = 1.3 to 3.6V, AVDD = 2.2 to 3.6V, VSS = AVSS = 0V, Ta = −20 to +70°C, Ta = −40 to +85°C for P version, unless otherwise

specified)

Parameter

Symbol

Condition

Rating

Unit

Min.

Typ.

Max.

SCLK input cycle

(slave mode)

tSCYC

When RC oscillation is active*

(VDD = 1.3 to 3.6V)



µs

When high-speed oscillation is

active*

3 (V

DD = 1.8 to 3.6V)



µs

SCLK output cycle

(master mode)

tSCYC



SCLK*



SCLK input pulse width

(slave mode)

tSW

When RC oscillation is active*

(VDD = 1.3 to 3.6V)



µs

When high-speed oscillation is

active*

3 (V

DD = 1.8 to 3.6V)

0.4



µs

SCLK output pulse width

(master mode)

tSW



SCLK*

×0.4

SCLK*

×0.5

SCLK*

×0.6

SOUT output delay time

(slave mode)

tSD

When RC oscillation is active*

(VDD = 1.3 to 3.6V)



500

When high-speed oscillation is

active*

3 (V

DD = 1.8 to 3.6V)



240

SOUT output delay time

(master mode)

tSD

When RC oscillation is active*

(VDD = 1.3 to 3.6V)



500

When high-speed oscillation is

active*

3 (V

DD = 1.8 to 3.6V)



240

SIN input

setup time

(slave mode)

tSS



SIN input

setup time

(master mode)

tSS

When RC oscillation is active*

(VDD = 1.3 to 3.6V)

500



When high-speed oscillation is

active*

3 (V

DD = 1.8 to 3.6V)

240



SIN input

hold time

tSH

When RC oscillation is active*

(VDD = 1.3 to 3.6V)

300



When high-speed oscillation is

active*

3 (V

DD = 1.8 to 3.6V)



1: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)

2: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0)

3: When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency

control register (FCON0)

tSD

SCLK0*

SIN0*

SOUT0*

*: Indicates the secondary function of the port.

tSD

tSS

tSH

tSW

tSCYC

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