MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2

12

Freescale Semiconductor

PLL Configuration

18

11000

68–132

204–396

2.5 (2)

3 (2)

19

11001

72–132

180–330

2 (2)

2.5 (2)

1A

11010

50–66

200–264

1 (4)

4 (2)

1B

68–132

204–396

2 (2)

3 (2)

1C

11100

66–99

198–297

1.5 (2)

3 (2)

1D

11101

72–99

180–248

1.5 (2)

2.5 (2)

1E (Rev. B)

Not usable

Off

Off

1E (Rev. D)

11110

66–114

231–399

2 (2)

3.5 (2)

1F

Not usable

Off

Off

Notes:

1.

Limited by maximum PCI input frequency (66 MHz).

2.

Limited by maximum system memory interface operating frequency (133 MHz).

3.

Limited by minimum memory VCO frequency (132 MHz).

4.

Limited due to maximum memory VCO frequency (372 MHz).

5.

Limited by maximum CPU operating frequency (400 MHz).

6.

Limited by minimum CPU VCO frequency (360 MHz).

7.

Limited by maximum CPU VCO frequency (800 MHz).

8.

Limited by minimum CPU operating frequency (100 MHz).

9.

Limited by minimum memory bus frequency (50 MHz).

10. In clock off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.

11. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for

clarity.

12. PLL_CFG[0:4] settings that are not listed are reserved.

13. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not

backwards-compatible.

14. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully

backwards-compatible.

15. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.

16. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral

logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for

hardware modeling support. The AC timing specifications given in this document do not apply in the PLL

bypass mode.

17. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the

peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In

this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode

operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be

externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications

given in this document do not apply in the dual PLL bypass mode.

Table 18. PLL Configurations for the 400-MHz Part Offering (continued)

Ref

PLL_CFG

Multipliers

PCI Clock Input

(PCI_SYNC_IN)

(MHz)

Periph

Logic/Mem

Bus Clock

Range

(MHz)

CPU Clock

Range

(MHz)

PCI-to-Mem

(Mem VCO)

Mem-to-CPU

(CPU VCO)