MPC8245 Part Number Specification for the MPC8245ARZUnnnX Series, Rev. 2

10

Freescale Semiconductor

General Parameters

4.3.3

Output AC Timing Specification

Table 11 provides the processor bus AC timing specification for output hold time for debug signals in the 466-MHz

timings assume a purely resistive 50-

Ω load (see Figure 14 in the MPC8245 Integrated Processor Hardware

Specifications). Output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias,

and connectors in the system. These specifications are for the default driver strengths listed in the MPC8245

Integrated Processor Hardware Specifications.

Table 11. Output AC Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

13b

Output hold (debug signals)

0.0

—

ns

1

Note:

1. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the

memory bus clock, SDRAM_SYNC_IN to the TTL level (0.8 or 2.0 V) of the signal in question. SDRAM_SYNC_IN is

the same as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising

edges occur on every rising and falling edge of PCI_SYNC_IN).