LMX2471 datasheet(18/36 Pages) NSC

18 / 36 page

Functional Description

1.0 GENERAL

The basic phase-lock-loop (PLL) configuration consists of a

high-stability crystal reference oscillator, a frequency synthe-

sizer such as the National Semiconductor LMX2471, a volt-

age controlled oscillator (VCO), and a passive loop filter. The

frequency synthesizer includes a phase detector, current

mode charge pump, as well as programmable reference [R]

and feedback [N] frequency dividers. The VCO frequency is

established by dividing the crystal reference signal down via

the R counter to obtain a frequency that sets the comparison

frequency. This comparison frequency, f

COMP, is input of a

phase/frequency detector and compared with another signal,

N, the feedback signal, which was obtained by dividing the

VCO frequency down by way of the N counter and fractional

circuitry. The phase/frequency detector’s current source out-

puts a charge into the loop filter, which is then converted into

the VCO’s control voltage. The function of the phase/

frequency comparator is to adjust the voltage presented to

the VCO until the frequency and phase of the feedback

signal match that of the reference signal. When this ‘phase-

locked’ condition exists, the VCO frequency will be N+F

times that of the comparison frequency, where N is the

integer component of the divide ratio and F is the fractional

component. Fractional synthesis allows the phase detector

frequency to be increased while maintaining the same fre-

quency step size for channel selection. The division value N

is thereby reduced giving a lower phase noise referred to the

phase detector input, and the comparison frequency is in-

creased allowing faster switching times.

1.1 PHASE DETECTOR OPERATING FREQUENCY

The maximum phase detector operating frequency for the

LMX2471 is 50 MHz. However, this is not possible in all

circumstances due to illegal divide ratios of the N counter.

The crystal reference frequency also limits the phase detec-

tor frequency. There are trade-offs in choosing what phase

detector frequency to operate at. If this frequency is run

higher, then phase noise will be lower, but lock time may be

increased due to cycle slipping. After this phase detector

frequency gets sufficiently high, then there are diminishing

returns for phase noise, and raising the charge pump current

has a greater impact on phase noise. This phase detector

frequency also has an impact on fractional spurs. In general,

the spur performance is better at higher phase detector

frequencies, although this is application specific. The current

consumption may also slightly increase with higher phase

detector frequencies.

1.2 OSCILLATOR

The LMX2471 provides maximum flexibility for choosing an

oscillator reference. One possible method is to use a single-

ended TCXO to drive the OSCin pin. The part can also be

configured to be driven differentially using the OSCin and

OSCout* pins. Note that the OSCin and OSCout* pins can

not be used as an inverter for a crystal. Selection between

these two modes does have a noticeable impact on phase

noise and sub-fractional spurs. Regardless of which mode is

used, the performance is generally best for higher oscillator

power levels.

1.3 POWER DOWN AND POWER UP MODES

The power down state of the LMX2471 is controlled by many

factors. The one factor that overrides all other factors is the

EN pin. If this pin is low, this guarantees the part will be

powered down. Asserting a high logic level on EN is neces-

sary to power up the chip, however, there are other bits in the

programming registers that can override this and put the PLL

back in a power down state. Provided that the voltage on the

EN pin is high, programming the RF_PD and IF_PD bits to

zero guarantees that the part will be powered up. Program-

ming either one of these bits to one will power down the

appropriate section of the synthesizer, provided that the

ATPU[1:0] ( Auto Power Up ) bits do not override this.

There are many different ways to power down this chip and

many different things that can be powered down. This sec-

tion discusses how to power down the PLLs on the chip.

There are two terms that need to be defined first: synchro-

nous power down and asynchronous power down. In the

case of synchronous power down, the PLL chip powers

down after the charge pump turns off. This is best to prevent

unwanted frequency glitches upon power up. However, in

certain cases where the charge pump is stuck on, such as

the case when there is no VCO signal applied, this type of

power down will not reliably work and asynchronous power

down is necessary. In the case of asynchronous power

down, the PLL powers down regardless of the status of the

charge pump. There are 4 factors that affect the power down

state of the chip: the EN pin, the power down bit, the TRI-

STATE bit, and writing to the RF N counter with the

RF_ATPU[1:0] bits enabled

EN Pin

ATPU[1:0] Bits Enabled +

RF N Counter Written To

RF_PD Bit

RF_CPT Bit

PLL State

Low

Asynchronous Power Down

High

Yes

PLL is active with charge pump in the active state.

High

PLL is active with charge pump in the active state.

High

PLL is active, but charge pump is TRI-STATE.

High

Synchronous Power Down

High

Asynchronous Power Down

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