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DM9301F датащи(PDF) 8 Page - List of Unclassifed Manufacturers

номер детали DM9301F
подробное описание детали  100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
PDF  22 Pages
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производитель  ETC [List of Unclassifed Manufacturers]
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DM9301F датащи(HTML) 8 Page - List of Unclassifed Manufacturers

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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
8
Final
Version: DM9301-DS-F02
May 8, 2000
Diagnostic Port Interface (Continued)
39, 40
MUXCTL1,
MUXCTL0
I
Mux. Control 1 and 0:
Used for testing the DM9301 Data Paths. Set to zero for
normal operation.
Initiated at a H/W reset. Active high.
MUXCTL1 MUXCTL0
DATA PATH
0
0
Normal, FX to TX and TX to FX
1
0
TX Transmit from TXD[4:0]
TXCLK from TX PLL
TX Receive to RXD[4:0]
RXCLK from TX receive clock
0
1
FX Transmit from TXD[4:0]
TXCLK from FX PLL
FX Receive to RXD[4:0]
RXCLK from FX receive clock
1
1
TX Transmit from TXD[4:0]
TXCLK from TX PLL
FX Receive to RXD[4:0]
RXCLK from FX receive clock
65, 54,
55, 57,
58, 60,
61
TPO6, TPO5,
TPO4, TPO3,
TPO2, TPO1,
TPO0
O
Test Port Output:
Reflects the DM9301 internal status. Selection of status
indicators is made by using TPEN and TPMUX.
Initiated at a H/W reset. Active high.
92, 91, 89,
88
TPI3, TPI2, TPI1,
TPI0,
I
Test Port Input:
Controls the DM9301 internal test features. Selection of
input control is made by using TPEN and TPMUX.
TPEN must be true (one) for this signal to take effect.
Initiated at a H/W reset. Active high.



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