DM9301F datasheet(7/22 Pages) ETC

7 / 22 page

DM9301

100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter

Final

Version: DM9301-DS-F02

May 8, 2000

LED Interface(Continued)

TXERRLED#

TX Error LED:

Indicates an error was detected by the TX Code Group

Alignment Monitor function on the TX receiver. Active

low (Open Drain Output)

The DM9301 incorporates a "monostable" function on

the TXERRLED output. This ensures that even

minimum size errors generate adequate LED ON to

insure visibility.

Diagnostic Port Interface

FXALPBK

FX Interface Analog Loop Back:

Loops the FX NRZI analog transmit data path to the FX

NRZI analog receive path.

Initiated at a H/W reset. Active high.

TXALPBK

TX Interface Analog Loop Back:

Loops the TX NRZI analog transmit data path to the TX

NRZI analog receive path.

Initiated at a H/W reset. Active high.

FXDLPBK

FX Interface Digital Loop Back:

Loops the FX 5-bit symbol digital transmit data path to

the FX 5-bit symbol digital receive path.

Initiated at a H/W reset. Active high.

TXDLPBK

TX Interface Digital Loop Back:

Loops the TX 5-bit symbol digital transmit data path to

the TX 5-bit symbol digital receive path.

Initiated at a H/W reset. Active high.

79, 77,

76, 74,

RXD0, RXD1,

RXD2, RXD3,

RXD4

Receive Data 4 through 0:

The receive data 5-bit symbol interface. Data is clocked

out on the falling edge of RXCLK.

RXCLK

Receive Clock:

25 Mhz recovered clock, clock source is selected by the

MUXCTL1 and MUXCTL0.

48, 47,

45, 44,

TXD0, TXD1,

TXD2, TXD3,

TXD4

Transmit Data 4 through 0:

The transmit data 5-bit symbol interface. Data is clocked

in on the rising edge of TXCLK.

TXCLK

Transmit Clock:

25 Mhz recovered clock, clock source is selected by the

MUXCTL1 and MUXCTL0.

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