AS3843N13 datasheet(18/20 Pages) ETC

18 / 20 page

ASTEC Semiconductor

latch is still fully operative, and the normal termi-

nation of this cycle by the current sense com-

parator will latch the output low until the

over-temperature condition is rectified. Cycling

the power will reset the over-temperature disable

mechanism, or the chip will re-start after cooling

through a nominal hysteresis band.

Section 2 Ð Design Considerations

2.1 Leading edge filter

The current sensed by R

S contains a leading

edge spike as shown in Figure 20. This spike is

caused by parasitic elements within the circuit

including the interwinding capacitance of the

power transformer and the recovery characteris-

tics of the rectifier diode(s). The spike, if not prop-

erly filtered, can cause stability problems by

prematurely terminating the output pulse.

A simple RC filter is used to suppress the spike.

The time constant should be chosen such that it

approximately equals the duration of the spike. A

good choice for R

1 is 1 k½, as this value is opti-

mum for the filter and at the same time, it simpli-

fies the determination of R

SLOPE (Section 2.2). If

the duration of the spike is, for example, 100 ns,

then C is determined by:

(6)

2.2 Slope compensation

Current-mode controlled converters can experi-

ence instabilities or subharmonic oscillations

AS384x

Current Mode Controller

AVG 2

AVG 1

(a)

∆I

(b)

∆I'

COMP

AVG 1 = IAVG 2

(c)

m = m

2/2

∆I

(d)

∆I'

COMP

m = m

2/2

Figure 22. Slope Compensation

Time Constant

100

Ω

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