AS3843N13 datasheet(14/20 Pages) ETC

14 / 20 page

ASTEC Semiconductor

and repeatable duty ratio clamping virtually

impossible due to other IC tolerances. The

AS3844/5 provides true 50% duty ratio clamping

by virtue of excluding from its flip-flop scheme,

the normal output blanking associated with the

discharge of C

Standard 3844/5 devices

include the output blanking associated with the

discharge of C

T, resulting in somewhat less than

a 50% duty ratio.

1.3.3 Synchronization

The advanced design of the AS3842 oscillator

simplifies synchronizing the frequency of two or

more devices to each other or to an external

clock. The R

T/CT doubles as a synchronization

input which can easily be driven from any open

collector logic output. Figure 16 shows some

simple circuits for implementing synchronization.

1.4 Error amplifier (COMP)

The AS3842 error amplifier is a wide bandwidth,

internally compensated operational amplifier

which provides a high DC open loop gain (90

dB). The input to the amplifier is a PNP differen-

tial pair. The non-inverting (+) input is internally

connected to the 2.5 V reference, and the invert-

ing (Ð) input is available at pin 2 (V

FB). The out-

put of the error amplifier consists of an active

pull-down and a 0.8 mA current source pull-up as

shown in Figure 17. This type of output stage

allows easy implementation of soft start, latched

shutdown and reduced current sense clamp

functions. It also permits wire ÒOR-ingÓ of the

error amplifier outputs of several 3842s, or com-

plete bypass of the error amplifier when its output

is forced to remain in its Òpull-upÓ condition.

AS384x

Current Mode Controller

–

COMPENSATION

NETWORK

2.50 V

PWM

E/A

COMP

0.8 mA

OUT

Figure 17. Error Amplifier Compensation

REG

AS3842

T/CT

GND

Open

Collector

Output

5 V

T/CT

Open

Collector

Output

3 K

2 K

T/CT

3 K

CMOS

SYNC

EXTERNAL CLOCK

Figure 16. Synchronization

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