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AT91SAM7A2 - Summary

6021AS–ATARM–03/04

Architectural

Overview

The AT91SAM7A2 architecture consists of two main buses, the Advanced System Bus (ASB)

and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It

interfaces the processor with the on-chip 32-bit memories and the external memories and

devices by means of the External Bus Interface (EBI). The APB is designed for access to on-

chip peripherals and is optimized for low power consumption. The AMBA

interface between the ASB and the APB.

The AT91SAM7A2 peripherals are designed to be programmed with a minimum number of

instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 1 Mbytes of

the 4 Gbyte address space. Except for the interrupt controller, the peripheral base address is

the lowest address of its memory space. The peripheral register set is composed of control,

mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, fre-

quently written registers are mapped into three memory locations. The first address is used to

set the individual register bits, the second resets the bits and the third address reads the value

stored in the register. A bit can be set or reset by writing a one to the corresponding position at

the appropriate address. Writing a zero has no effect. Individual bits can thus be modified with-

out having to use costly read-modify-write and complex bit manipulation instructions.

The ARM7TDMI processor operates in little-endian mode in the AT91SAM7A2 microcontrol-

ler. The processor's internal architecture and the ARM and Thumb instruction sets are

described in the ARM7TDMI Datasheet.

AMC: Advanced

Memory Controller

The AT91SAM7A2 embeds 16 Kbytes of internal SRAM. The internal memory is directly con-

nected to the 32-bit data bus and is single-cycle accessible. This provides maximum

performance of 27 MIPS @ 30 MHz by using the ARM® instruction set of the processor, mini-

mizing system power consumption and improving on the performance of separate memory

solutions.

EBI: External Bus

Interface

The EBI generates the signals which control the accesses to the external memories or periph-

eral devices. The EBI is fully programmable and can address up to 6 Mbytes. It has four chip

selects and a 21-bit address bus, the upper bit of which is multiplexed with a chip select. Sep-

arate read and write control signals allow for direct memory and peripheral interfacing. The

EBI supports different access protocols allowing single clock cycle memory accesses. The

main features are:

•

External Memory Mapping

•

Up to Four Chip Select Lines

•

Byte Write or Byte Select Lines

•

8-bit or 16-bit Data Bus

•

External Wait

•

Remap of Boot Memory

•

Two Different Read Protocols

•

Programmable Wait State Generation

GIC: Generic

Interrupt

Controller

The AT91SAM7A2 has an 8-level priority, individually maskable, vectored interrupt controller.

This feature substantially reduces the software and real time overhead in handling internal and

external interrupts. The interrupt controller is connected to the nFIQ (fast interrupt request)

and the nIRQ (standard interrupt request) inputs of the ARM7TDMI™ processor. The proces-

sor's nFIQ line can only be asserted by the external fast interrupt request input: FIQ. The nIRQ

line can be asserted by the interrupts generated by the on-chip peripherals and the external

interrupt request lines: IRQ0 to IRQ1. An 8-level priority encoder allows the customer to define

the priority between the different nIRQ interrupt sources. Internal sources are programmed to