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AT91SAM7A2 - Summary

6021AS–ATARM–03/04

ADC: Analog to

Digital Converter

The two identical 8-channel 10-bit Analog-to-Digital Converters (ADC) are based on a Succes-

sive Approximation Register (SAR) approach. Each ADC has 8 analog input pins, ANA0IN0 to

ANA0IN7 and ANA1IN0 to ANA1IN7, and provides an interrupt signal to the AIC. Both ADCs

The ADC can be configured to automatically enter Sleep Mode after a conversion sequence,

and can be triggered by the software. The ADC allows a data transfer with the PDC.

PMC: Power

Management

Controller

The AT91SAM7A2 Power Management Controller allows optimization of power consumption.

The PMC enables/disables the clock inputs of the PDC and ARM core. Moreover, the main

oscillator, the PLL and the analog peripherals can be put in standby mode allowing minimum

power consumption to be obtained. The PMC provides the following operating modes:

•

Normal: the clock generator provides clock to chip.

•

Wait Mode: the ARM core clock is deactivated.

•

Slow Mode: the clock generator is deactivated, the system is clocked at 32.768 kHz.

Each peripheral clock can be independently stopped or started directly in the peripheral to fur-

ther reduce power consumption in Normal, Wait and Slow Modes.

ICE Debug Mode

ARM Standard Embedded In Circuit Emulation is supported via the ICE port. It is connected to

a host computer via an external ICE Interface. In ICE Debug Mode the ARM core responds

with a non-JTAG chip ID which identifies the core to the ICE system. This is not JTAG IEEE

1149.1 compliant.