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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADUC832 датащи(PDF) 21 Page - Analog Devices |
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ADUC832 датащи(HTML) 21 Page - Analog Devices |
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21 / 80 page  REV. 0 ADuC832 –21– ADCCON3 – (ADC Control SFR #3) The ADCCON3 register controls the operation of various calibra- tion modes as well as giving an indication of ADC busy status. SFR Address: F5H SFR Power-On Default Value: 00H Bit Addressable: NO Table V. ADCCON3 SFR Bit Designations Bit Name Description ADCCON3.7 BUSY The ADC Busy Status Bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration. ADCCON3.6 GNCLD Gain Calibration Disable Bit. Set to “0” to Enable Gain Calibration. Set to “1” to Disable Gain Calibration. ADCCON3.5 AVGS1 Number of Averages Selection Bits. ADCCON3.4 AVGS0 This bit selects the number of ADC readings averaged during a calibration cycle. AVGS1 AVGS0 Number of Averages 0 0 15 0 1 1 1 0 31 1 1 63 ADCCON3.3 RSVD Reserved. This bit should always be written as “0.” ADCCON3.2 RSVD This bit should always be written as “1” by the user when performing calibration. ADCCON3.1 TYPICAL Calibration Type Select Bit. This bit selects between Offset (zero-scale) and Gain (full-scale) calibration. Set to “0” for Offset Calibration. Set to “1” for Gain Calibration. ADCCON3.0 SCAL Start Calibration Cycle Bit. When set, this bit starts the selected calibration cycle. It is automatically cleared when the calibration cycle is completed. |
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