TSB81BA3IPFPEP datasheet(49/61 Pages) TI1

49 / 61 page

TSB81BA3D, TSB81BA3DI

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

SLLS559E − DECEMBER 2002 − REVISED JUNE 2006

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION (1394B INTERFACE)

receive

When the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive

on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start

of a packet by placing the speed code (encoded as shown in Table 35) on the D terminals, followed by packet

data. The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been

transferred. The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received

packets are transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included

in the calculation of CRC or any other data protection mechanisms.

The PHY may optionally send status information to the LLC at anytime during the data-on indication. Only bus

status transfer information can be sent during a data-on indication. The PHY holds the CTL terminals in the

status state for 1 PCLK cycle and modify the D terminals to the correct status state. Note that the status transfer

during the data-on indication does not need to be preceded or followed by a data-on indication.

It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus followed

by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed exceeds

the capability of the receiving PHY, or whenever the LLC immediately releases the bus without transmitting any

data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all 1s) on the D

terminals, followed by Idle on the CTL terminals, without any speed code or data being transferred. In all cases,

in normal operation, the TSB81BA3D sends at least one data-on indication before sending the speed code or

terminating the receive operation.

The TSB81BA3D also transfers its own self-ID packet, transmitted during the self-ID phase of bus initialization,

to the LLC. This packet it transferred to the LLC just as any other received self-ID packet.

SPD

(a)

(b)

FF (data-on)

D0–D7

CTL0, CTL1

PCLK

(c)

(d)

(e)

NOTE A: SPD = Speed code, see Table 35. d0–dn = Packet data

Figure 24. Normal Packet Reception Timing

TSB81BA3IPFPEP датащи(PDF) 49 Page - Texas Instruments